<p>Philipp Deppenwiese <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/25426">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Philipp Deppenwiese: Looks good to me, approved
Lijian Zhao: Looks good to me, but someone else must approve
Evandro Luiz Hauenstein: Looks good to me, but someone else must approve
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/denverton_ns: Enable common block PMC<br><br>Mainly update headers to build.<br><br>Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove<br>function configuring the global reset through PMC base.<br>On denverton the global reset lock is not in PMC base<br>but in the PCI registers so this code cannot be shared.<br><br>Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>Reviewed-on: https://review.coreboot.org/25426<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Lijian Zhao <lijian.zhao@intel.com><br>Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com><br>Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com><br>---<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/common/block/pmc/Kconfig<br>M src/soc/intel/common/block/pmc/pmclib.c<br>M src/soc/intel/denverton_ns/Kconfig<br>M src/soc/intel/denverton_ns/acpi.c<br>M src/soc/intel/denverton_ns/include/soc/iomap.h<br>M src/soc/intel/denverton_ns/include/soc/pm.h<br>M src/soc/intel/denverton_ns/include/soc/pmc.h<br>M src/soc/intel/denverton_ns/pmutil.c<br>M src/soc/intel/skylake/Kconfig<br>11 files changed, 38 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig</span><br><span>index 4dcecf5..fbc81ce 100644</span><br><span>--- a/src/soc/intel/apollolake/Kconfig</span><br><span>+++ b/src/soc/intel/apollolake/Kconfig</span><br><span>@@ -61,6 +61,7 @@</span><br><span> select POSTCAR_CONSOLE</span><br><span> select POSTCAR_STAGE</span><br><span> select PMC_INVALID_READ_AFTER_WRITE</span><br><span style="color: hsl(120, 100%, 40%);">+ select PMC_GLOBAL_RESET_ENABLE_LOCK</span><br><span> select REG_SCRIPT</span><br><span> select RTC</span><br><span> select SMM_TSEG</span><br><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 3392728..256cf1b 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -53,6 +53,7 @@</span><br><span> select SMM_TSEG</span><br><span> select SMP</span><br><span> select SOC_AHCI_PORT_IMPLEMENTED_INVERT</span><br><span style="color: hsl(120, 100%, 40%);">+ select PMC_GLOBAL_RESET_ENABLE_LOCK</span><br><span> select SOC_INTEL_COMMON</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span>diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig</span><br><span>index 46f134e..2f08408 100644</span><br><span>--- a/src/soc/intel/common/block/pmc/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/pmc/Kconfig</span><br><span>@@ -37,3 +37,11 @@</span><br><span> help</span><br><span> Enable this for PMC devices where a read back of ACPI BAR and</span><br><span> IO access bit does not return the previously written value.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config PMC_GLOBAL_RESET_ENABLE_LOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable this for PMC devices where the reset configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ and lock register is located under PMC BASE at offset ETR.</span><br><span style="color: hsl(120, 100%, 40%);">+ Note that the reset register is still at 0xCF9 this only</span><br><span style="color: hsl(120, 100%, 40%);">+ controls the enable and lock feature.</span><br><span>diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>index 339e674..52bfaec 100644</span><br><span>--- a/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>+++ b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>@@ -419,6 +419,7 @@</span><br><span> return ps->prev_sleep_state;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK)</span><br><span> /*</span><br><span> * If possible, lock 0xcf9. Once the register is locked, it can't be changed.</span><br><span> * This lock is reset on cold boot, hard reset, soft reset and Sx.</span><br><span>@@ -451,6 +452,7 @@</span><br><span> reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;</span><br><span> write32((void *)etr, reg);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK</span><br><span> </span><br><span> int vboot_platform_is_resuming(void)</span><br><span> {</span><br><span>diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig</span><br><span>index 4517065..e22b8ee 100644</span><br><span>--- a/src/soc/intel/denverton_ns/Kconfig</span><br><span>+++ b/src/soc/intel/denverton_ns/Kconfig</span><br><span>@@ -46,6 +46,8 @@</span><br><span> select INTEL_DESCRIPTOR_MODE_CAPABLE</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES</span><br><span> # select SOC_INTEL_COMMON_BLOCK_SA</span><br><span> select SOC_INTEL_COMMON_BLOCK_FAST_SPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_GPIO</span><br><span>diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c</span><br><span>index 07278c5..6a947ff 100644</span><br><span>--- a/src/soc/intel/denverton_ns/acpi.c</span><br><span>+++ b/src/soc/intel/denverton_ns/acpi.c</span><br><span>@@ -130,7 +130,7 @@</span><br><span> fadt->pm1b_cnt_blk = 0x0;</span><br><span> fadt->pm2_cnt_blk = pmbase + PM2_CNT;</span><br><span> fadt->pm_tmr_blk = pmbase + PM1_TMR;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe0_blk = pmbase + GPE0_STS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe0_blk = pmbase + GPE0_STS(GPE_STD);</span><br><span> fadt->gpe1_blk = 0;</span><br><span> </span><br><span> /* Control Registers - Length */</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>index 29b231f..a7548d4 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>@@ -29,6 +29,7 @@</span><br><span> /* Southbridge internal device IO BARs (Set to match FSP settings) */</span><br><span> #define DEFAULT_PMBASE 0x1800</span><br><span> #define DEFAULT_ACPI_BASE DEFAULT_PMBASE</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_BASE_ADDRESS DEFAULT_PMBASE</span><br><span> #define DEFAULT_TCO_BASE 0x400</span><br><span> </span><br><span> /* Southbridge internal device MEM BARs (Set to match FSP settings) */</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h</span><br><span>index 2dc8781..32d8a76 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/pm.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/pm.h</span><br><span>@@ -20,10 +20,9 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <soc/pmc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SLEEP_STATE_S0 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define SLEEP_STATE_S3 3</span><br><span style="color: hsl(0, 100%, 40%);">-#define SLEEP_STATE_S5 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_MAX 127</span><br><span> </span><br><span> struct chipset_power_state {</span><br><span> uint16_t pm1_sts;</span><br><span>@@ -31,8 +30,8 @@</span><br><span> uint32_t pm1_cnt;</span><br><span> uint16_t tco1_sts;</span><br><span> uint16_t tco2_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_sts[4];</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_en[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_sts[GPE0_REG_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en[GPE0_REG_MAX];</span><br><span> uint32_t gen_pmcon_a;</span><br><span> uint32_t gen_pmcon_b;</span><br><span> uint32_t gblrst_cause[2];</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h</span><br><span>index edb5c55..4db3981 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/pmc.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/pmc.h</span><br><span>@@ -120,7 +120,10 @@</span><br><span> #define GPE_CTRL 0x40</span><br><span> #define SWGPE_CTRL (1 << 17)</span><br><span> #define PM2_CNT 0x50</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPE0_STS 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_REG_MAX 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_REG_SIZE 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_STS(x) (0x80 + (x * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_STD 0</span><br><span> #define GPIO31_STS (1 << 31)</span><br><span> #define GPIO30_STS (1 << 30)</span><br><span> #define GPIO29_STS (1 << 29)</span><br><span>@@ -166,7 +169,7 @@</span><br><span> #define IE_SCI_STS (1 << 3)</span><br><span> #define SWGPE_STS (1 << 2)</span><br><span> #define HOT_PLUG_STS (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPE0_EN 0x90</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_EN(x) (0x90 + (x * 4))</span><br><span> #define GPIO31_EN (1 << 31)</span><br><span> #define GPIO30_EN (1 << 30)</span><br><span> #define GPIO29_EN (1 << 29)</span><br><span>@@ -236,6 +239,12 @@</span><br><span> #define TCO2_CNT 0x0a</span><br><span> #define TCO_TMR 0x12</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRSTS 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_GPE_CFG 0x120</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DWX_MASK 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW_SHIFT(x) (4 + 4*(x))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* I/O ports */</span><br><span> #define RST_CNT 0xcf9</span><br><span> #define FULL_RST (1 << 3)</span><br><span>diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c</span><br><span>index 78903bb..ccf0d95 100644</span><br><span>--- a/src/soc/intel/denverton_ns/pmutil.c</span><br><span>+++ b/src/soc/intel/denverton_ns/pmutil.c</span><br><span>@@ -189,17 +189,17 @@</span><br><span> void enable_gpe(uint32_t mask)</span><br><span> {</span><br><span> uint16_t pmbase = get_pmbase();</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));</span><br><span> gpe0_en |= mask;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));</span><br><span> }</span><br><span> </span><br><span> void disable_gpe(uint32_t mask)</span><br><span> {</span><br><span> uint16_t pmbase = get_pmbase();</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));</span><br><span> gpe0_en &= ~mask;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));</span><br><span> }</span><br><span> </span><br><span> void disable_all_gpe(void) { disable_gpe(~0); }</span><br><span>@@ -207,8 +207,8 @@</span><br><span> static uint32_t reset_gpe_status(void)</span><br><span> {</span><br><span> uint16_t pmbase = get_pmbase();</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS));</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS));</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));</span><br><span> return gpe_sts;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index 9a5aae4..614c251 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -51,6 +51,7 @@</span><br><span> select SA_ENABLE_DPR</span><br><span> select SMM_TSEG</span><br><span> select SMP</span><br><span style="color: hsl(120, 100%, 40%);">+ select PMC_GLOBAL_RESET_ENABLE_LOCK</span><br><span> select SOC_INTEL_COMMON</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25426">change 25426</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd </div>
<div style="display:none"> Gerrit-Change-Number: 25426 </div>
<div style="display:none"> Gerrit-PatchSet: 6 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>
<div style="display:none"> Gerrit-Reviewer: David Guckian <david.guckian@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Evandro Luiz Hauenstein <kingsumos@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert@online.net> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Shine Liu <shine.liu@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-CC: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-CC: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-CC: Jay Talbott <JayTalbott@sysproconsulting.com> </div>