<p>Philipp Hug has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28602">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/sifive/fu540: Switch clock to 1GHz in romstage<br><br>Invoke clock_init in romstage for SiFive Unleashed.<br>Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389<br>---<br>M src/mainboard/sifive/hifive-unleashed/romstage.c<br>M src/soc/sifive/fu540/Makefile.inc<br>M src/soc/sifive/fu540/clock.c<br>3 files changed, 45 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28602/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c</span><br><span>index ea6efb9..9729f86 100644</span><br><span>--- a/src/mainboard/sifive/hifive-unleashed/romstage.c</span><br><span>+++ b/src/mainboard/sifive/hifive-unleashed/romstage.c</span><br><span>@@ -13,8 +13,13 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/streams.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/uart.h></span><br><span> #include <program_loading.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/sdram.h></span><br><span> </span><br><span> void main(void)</span><br><span> {</span><br><span>@@ -22,5 +27,18 @@</span><br><span> </span><br><span> /* TODO: Follow Section 6.3 (FSBL) of the FU540 manual */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Flush console before changing clock/UART divisor to prevent garbage</span><br><span style="color: hsl(120, 100%, 40%);">+ * being printed.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ console_tx_flush();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // re-initialize UART</span><br><span style="color: hsl(120, 100%, 40%);">+ #if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_init(CONFIG_UART_FOR_CONSOLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> run_ramstage();</span><br><span> }</span><br><span>diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc</span><br><span>index b991783..ed1836e 100644</span><br><span>--- a/src/soc/sifive/fu540/Makefile.inc</span><br><span>+++ b/src/soc/sifive/fu540/Makefile.inc</span><br><span>@@ -22,6 +22,7 @@</span><br><span> romstage-y += media.c</span><br><span> romstage-y += sdram.c</span><br><span> romstage-y += otp.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += clock.c</span><br><span> </span><br><span> ramstage-y += uart.c</span><br><span> ramstage-y += clint.c</span><br><span>@@ -29,6 +30,7 @@</span><br><span> ramstage-y += sdram.c</span><br><span> ramstage-y += cbmem.c</span><br><span> ramstage-y += otp.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += clock.c</span><br><span> </span><br><span> CPPFLAGS_common += -Isrc/soc/sifive/fu540/include</span><br><span> </span><br><span>diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c</span><br><span>index a98a093..5fcf5bd 100644</span><br><span>--- a/src/soc/sifive/fu540/clock.c</span><br><span>+++ b/src/soc/sifive/fu540/clock.c</span><br><span>@@ -198,8 +198,33 @@</span><br><span> / (1ul << divq);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define FU540_UART_DEVICES 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define FU540_UART_REG_DIV 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define FU540_UART_DIV_VAL 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FU540_SPI_DIV 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define FU540_SPI_DIV_VAL 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void static update_peripheral_clock_dividers(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((uint32_t *)(FU540_QSPI0 + FU540_SPI_DIV), FU540_SPI_DIV_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((uint32_t *)(FU540_QSPI1 + FU540_SPI_DIV), FU540_SPI_DIV_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((uint32_t *)(FU540_QSPI2 + FU540_SPI_DIV), FU540_SPI_DIV_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t i = 0; i < FU540_UART_DEVICES; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((uint32_t *)(FU540_UART(i) + FU540_UART_REG_DIV), FU540_UART_DIV_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void clock_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Update the peripheral clock dividers of UART, SPI and I2C to safe</span><br><span style="color: hsl(120, 100%, 40%);">+ * values as we can't put them in reset before changing frequency.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ update_peripheral_clock_dividers();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> init_coreclk();</span><br><span> </span><br><span> // put DDR and ethernet in reset</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28602">change 28602</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28602"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 </div>
<div style="display:none"> Gerrit-Change-Number: 28602 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Hug <philipp@hug.cx> </div>