<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28596">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/asrock/g41m_vs3_r2: Add mainboard<br><br>The following was tested:<br>- CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set)<br>- The VGA output with native graphic init<br>- USB<br>- COM1<br>- Ethernet<br>- SATA<br>- PCIe<br>- PCI<br><br>Has the following problems:<br>- The Ethernet NIC is not usable after S3 resume and requires Linux to reload<br> the driver. Vendor firmware also has this problem so it is quite likely it<br> is just a atl1c driver problem.<br><br>TODO: Add documentation<br><br>Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/asrock/g41c-gs/Kconfig<br>M src/mainboard/asrock/g41c-gs/Kconfig.name<br>M src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl<br>M src/mainboard/asrock/g41c-gs/gpio.c<br>A src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb<br>5 files changed, 196 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28596/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig</span><br><span>index ad2fe22..e2ad83b 100644</span><br><span>--- a/src/mainboard/asrock/g41c-gs/Kconfig</span><br><span>+++ b/src/mainboard/asrock/g41c-gs/Kconfig</span><br><span>@@ -14,7 +14,7 @@</span><br><span> # GNU General Public License for more details.</span><br><span> #</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_VS3_R2_0</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS</span><br><span> def_bool y</span><br><span>@@ -24,7 +24,7 @@</span><br><span> select SOUTHBRIDGE_INTEL_I82801GX</span><br><span> select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0</span><br><span> select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS \</span><br><span style="color: hsl(0, 100%, 40%);">- || BOARD_ASROCK_G41M_GS</span><br><span style="color: hsl(120, 100%, 40%);">+ || BOARD_ASROCK_G41M_GS || BOARD_ASROCK_G41M_VS3_R2_0</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select BOARD_ROMSIZE_KB_1024</span><br><span> select PCIEXP_ASPM</span><br><span>@@ -46,12 +46,14 @@</span><br><span> default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0</span><br><span> default "G41C-GS" if BOARD_ASROCK_G41C_GS</span><br><span> default "G41M-GS" if BOARD_ASROCK_G41M_GS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "G41M-VS3 R2.0" if BOARD_ASROCK_G41M_VS3_R2_0</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span> default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0</span><br><span> default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS</span><br><span> default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/g41m-vs3-r2/devicetree.cb" if BOARD_ASROCK_G41M_VS3_R2_0</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name</span><br><span>index 329a3e2..e10558c 100644</span><br><span>--- a/src/mainboard/asrock/g41c-gs/Kconfig.name</span><br><span>+++ b/src/mainboard/asrock/g41c-gs/Kconfig.name</span><br><span>@@ -6,3 +6,6 @@</span><br><span> </span><br><span> config BOARD_ASROCK_G41M_GS</span><br><span> bool "G41M-GS"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_ASROCK_G41M_VS3_R2_0</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "G41M-VS3 R2.0"</span><br><span>diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl</span><br><span>index bb8745e..21cec96 100644</span><br><span>--- a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl</span><br><span>+++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl</span><br><span>@@ -18,6 +18,9 @@</span><br><span> * IRQ routing for the 0:1e.0 PCI bridge of the ICH7</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)</span><br><span style="color: hsl(120, 100%, 40%);">+ || IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS)</span><br><span style="color: hsl(120, 100%, 40%);">+ || IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)</span><br><span> If (PICM) {</span><br><span> Return (Package() {</span><br><span> /* PCI1 SLOT 1 */</span><br><span>@@ -51,3 +54,38 @@</span><br><span> /* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */</span><br><span> })</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#else /* BOARD_ASROCK_G41M_VS3_R2_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI1 SLOT 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 0, 0, 0x11},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 1, 0, 0x12},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 2, 0, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 3, 0, 0x10},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI1 SLOT 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, 0, 0x17},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 1, 0, 0x14},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 2, 0, 0x15},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 3, 0, 0x16},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* device not in lspci but in vendor DSDT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Package() { 0x0008ffff, 0, 0, 0x14}, */</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+} Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* device not in lspci but in vendor DSDT */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/asrock/g41c-gs/gpio.c b/src/mainboard/asrock/g41c-gs/gpio.c</span><br><span>index b6ccbad..3508950 100644</span><br><span>--- a/src/mainboard/asrock/g41c-gs/gpio.c</span><br><span>+++ b/src/mainboard/asrock/g41c-gs/gpio.c</span><br><span>@@ -40,8 +40,13 @@</span><br><span> .gpio0 = GPIO_DIR_INPUT,</span><br><span> .gpio6 = GPIO_DIR_INPUT,</span><br><span> .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0)</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> .gpio8 = GPIO_DIR_INPUT,</span><br><span> .gpio9 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> .gpio10 = GPIO_DIR_OUTPUT,</span><br><span> .gpio12 = GPIO_DIR_INPUT,</span><br><span> .gpio13 = GPIO_DIR_INPUT,</span><br><span>@@ -67,6 +72,10 @@</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)</span><br><span> static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0)</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> .gpio10 = GPIO_LEVEL_LOW,</span><br><span> .gpio15 = GPIO_LEVEL_LOW,</span><br><span> .gpio16 = GPIO_LEVEL_HIGH,</span><br><span>diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..2b0da8f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb</span><br><span>@@ -0,0 +1,142 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+# (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/x4x # Northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on # APIC cluster</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_1067x # CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xACAC off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on # PCI domain</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1458 0x5000 inherit</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x2e30</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.0 on end # PEG</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 on # Integrated graphics controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x2e32</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.0 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.1 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/i82801gx # Southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ide_enable_primary" = "0x1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_en" = "0x440"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x3662</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # PCIe 2 (ethernet)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCIe 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCIe 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCIe 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27c8</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27c9</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27ca</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27cb</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 on # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27cc</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 off end # AC'97 Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # AC'97 Modem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # ISA bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27b8</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/winbond/w83627dhg</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end # Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # Parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ # global</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x28 = 0x70</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2c = 0xd2</span><br><span style="color: hsl(120, 100%, 40%);">+ # parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off end # COM2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # Keyboard & MOUSE</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x72 = 0x0C</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 off end # SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off end # GPIO6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # WDT0#, PLED</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.9 on end # GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.109 off end # GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.209 on # GPIO4</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf4 = 0xb3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.309 off end # GPIO5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a on # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe4 = 0x10 # Power dram during s3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HWM, front pannel LED</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x290</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.c off end # PECI, SST</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on # PATA/IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27df</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27c0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on # SMbus</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x1849 0x27da</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/ck505 # W83115RG-965</span><br><span style="color: hsl(120, 100%, 40%);">+ # set SATA to fixed 100Mhz refclk</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mask" = "{ 0x02 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "regs" = "{ 0x02 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 69 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28596">change 28596</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28596"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f </div>
<div style="display:none"> Gerrit-Change-Number: 28596 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>