<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28577">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Program read training results to all ranks<br><br>While during the read training itself only the settings for rank 0 are used for<br>all ranks, the controller does use the separate settings for each rank later on.<br>It is unknown which register is responsible for this.<br>Therefore program the results for all ranks.<br><br>TESTED: Fixes DG43GT not booting with only the second DIMM slot of a channel<br>populated.<br><br>Change-Id: I7965a068ef4779847e62e966154764370c91302a<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/northbridge/intel/x4x/dq_dqs.c<br>1 file changed, 7 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28577/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c</span><br><span>index 8704d39..e4aacfa 100644</span><br><span>--- a/src/northbridge/intel/x4x/dq_dqs.c</span><br><span>+++ b/src/northbridge/intel/x4x/dq_dqs.c</span><br><span>@@ -447,7 +447,10 @@</span><br><span> * - use the mean between the saved succeeding and failing value</span><br><span> * - note0: bytelanes cannot be trained independently, so the delays need to be</span><br><span> * adjusted and tested for all of them at the same time</span><br><span style="color: hsl(0, 100%, 40%);">- * - note1: this memory controller appears to have per rank registers for these</span><br><span style="color: hsl(120, 100%, 40%);">+ * - note1: At this stage all ranks effectively use the rank0's rt_dqs settings,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but later on their respective setting is used (TODO where??).</span><br><span style="color: hsl(120, 100%, 40%);">+ * So programming the results for all ranks at the end of the training.</span><br><span style="color: hsl(120, 100%, 40%);">+ * - note2: this memory controller appears to have per rank registers for these</span><br><span> * DQS rx delays, but only the one rank 0 seems to be used for all of them</span><br><span> */</span><br><span> int do_read_training(struct sysinfo *s)</span><br><span>@@ -498,6 +501,8 @@</span><br><span> }</span><br><span> </span><br><span> printk(RAM_DEBUG, "Centered values, loop %d:\n", loop);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Later on separate settings for each rank are used so program</span><br><span style="color: hsl(120, 100%, 40%);">+ all of them */</span><br><span> FOR_EACH_BYTELANE(lane) {</span><br><span> u8 center = (dqs_lower[lane] + dqs_upper[lane]) / 2;</span><br><span> printk(RAM_DEBUG, "\t lane%d: #%d\n", lane, center);</span><br><span>@@ -519,7 +524,7 @@</span><br><span> printk(BIOS_ERR,</span><br><span> "Huh? read training overflowed!!\n");</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank)</span><br><span style="color: hsl(120, 100%, 40%);">+ FOR_EACH_RANK_IN_CHANNEL(rank)</span><br><span> rt_set_dqs(channel, lane, rank,</span><br><span> &s->rt_dqs[channel][lane]);</span><br><span> printk(BIOS_DEBUG, "\tlane%d: %d.%d\n",</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28577">change 28577</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28577"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7965a068ef4779847e62e966154764370c91302a </div>
<div style="display:none"> Gerrit-Change-Number: 28577 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>