<p>Caveh Jalali would like caveh jalali to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/28535">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variants/atlas: enable NVMe<br><br>This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and<br>clock#4.<br><br>BUG=b:113369699<br>TEST=booted on atlas<br><br>Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8<br>Signed-off-by: Caveh Jalali <caveh@chromium.org><br>---<br>M src/mainboard/google/poppy/variants/atlas/devicetree.cb<br>M src/mainboard/google/poppy/variants/atlas/gpio.c<br>2 files changed, 18 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28535/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>index c96081c..968faef 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>@@ -147,7 +147,7 @@</span><br><span> .dc_loadline = 441,</span><br><span> }"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # PCIe Root port 1 with SRCCLKREQ1#</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe Root port 1 with SRCCLKREQ1# (WLAN)</span><br><span> register "PcieRpEnable[0]" = "1"</span><br><span> register "PcieRpClkReqSupport[0]" = "1"</span><br><span> register "PcieRpClkReqNumber[0]" = "1"</span><br><span>@@ -155,6 +155,20 @@</span><br><span> register "PcieRpAdvancedErrorReporting[0]" = "1"</span><br><span> register "PcieRpLtrEnable[0]" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe Root port 5 (NVMe)</span><br><span style="color: hsl(120, 100%, 40%);">+ # PcieRpEnable: Enable root port</span><br><span style="color: hsl(120, 100%, 40%);">+ # PcieRpClkReqSupport: Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ # PcieRpClkReqNumber: Uses SRCCLKREQ4#</span><br><span style="color: hsl(120, 100%, 40%);">+ # PcieRpClkSrcNumber: Uses CLKOUT_PCIE_4</span><br><span style="color: hsl(120, 100%, 40%);">+ # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[4]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # USB 2.0</span><br><span> register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1</span><br><span> register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty</span><br><span>@@ -329,7 +343,7 @@</span><br><span> device pci 1c.1 off end # PCI Express Port 2</span><br><span> device pci 1c.2 off end # PCI Express Port 3</span><br><span> device pci 1c.3 off end # PCI Express Port 4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.4 off end # PCI Express Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCI Express Port 5 (NVMe)</span><br><span> device pci 1c.5 off end # PCI Express Port 6</span><br><span> device pci 1c.6 off end # PCI Express Port 7</span><br><span> device pci 1c.7 off end # PCI Express Port 8</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c</span><br><span>index 5f1a1f5..f82976e 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/atlas/gpio.c</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c</span><br><span>@@ -78,8 +78,8 @@</span><br><span> PAD_CFG_NC(GPP_B7),</span><br><span> /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */</span><br><span> PAD_CFG_GPO(GPP_B8, 0, RSMRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B9 : SRCCLKREQ4# ==> NC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NC(GPP_B9),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B9 : SRCCLKREQ4# ==> NVME_PCIE_CLKREQ_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),</span><br><span> /* B10 : SRCCLKREQ5# ==> NC */</span><br><span> PAD_CFG_NC(GPP_B10),</span><br><span> /* B11 : EXT_PWR_GATE# ==> NC */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28535">change 28535</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 </div>
<div style="display:none"> Gerrit-Change-Number: 28535 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Caveh Jalali <caveh@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: caveh jalali <caveh@chromium.org> </div>