<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/28468">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/include: Add CPER definitions<br><br>Add definitions from the UEFI appendix on Common Platform Error<br>Record (appx. N in revision 2.7-A). The structures and fields<br>defined are the minimum required for generating ACPI Boot Error<br>Record data in a subsequent patch.<br><br>BUG=b:65446699<br>TEST=inspect BERT region, and dmesg, on full patch stack. Use test<br> data plus a failing Grunt system.<br><br>Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>Reviewed-on: https://review.coreboot.org/28468<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Martin Roth <martinroth@google.com><br>---<br>A src/include/cper.h<br>1 file changed, 507 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/include/cper.h b/src/include/cper.h</span><br><span>new file mode 100644</span><br><span>index 0000000..88c7cba</span><br><span>--- /dev/null</span><br><span>+++ b/src/include/cper.h</span><br><span>@@ -0,0 +1,507 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _CPER_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _CPER_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <uuid.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <bcd.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* This file contains some definitions and helpers for implementing structures</span><br><span style="color: hsl(120, 100%, 40%);">+ * in the UEFI specification, Appendix "Common Platform Error Record". This</span><br><span style="color: hsl(120, 100%, 40%);">+ * is not a complete definition, but contains enough to generate a BERT ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * table.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * All table numbers and references correspond with UEFI spec version 2.7,</span><br><span style="color: hsl(120, 100%, 40%);">+ * errata A, available at uefi.org.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Error Record Header, Timestamp field (Table 251) */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct cper_timestamp { /* BCD values */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 sec;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 min;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 hour;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 precise; /* b[0] precise - timestamp of error, b[7:1] rsvd */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 day;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 month;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 year;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 century;</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed cper_timestamp_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_TIMESTAMP_PRECISE BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Section Descriptor, Flags field (Table 253) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PRIMARY BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_CONTAINMENT_WARNING BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_RESET BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_ERROR_THRESHOLD_EXCEEDED BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_RESOURCE_NOT_ACCESSIBLE BIT(4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_LATENT_ERROR BIT(5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PROPAGATED BIT(6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_OVERFLOW BIT(7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Section Descriptor, Section Types values (Table 253) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PROC_GENERIC_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0x9876ccad, 0x47b4, 0x4bdb, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PROC_IA32X64_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0xdc3ea0b0, 0xa144, 0x4797, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xb9, 0x5b, 0x53, 0xfa, 0x24, 0x2b, 0x6e, 0x1d)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PROC_ARM_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0xe19e3d16, 0xbc11, 0x11e4, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PLATFORM_MEM_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0xa5bc1114, 0x6f64, 0x4ede, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PLATFORM_MEM2_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0x61ec04fc, 0x48e6, 0xd813, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x25, 0xc9, 0x8d, 0xaa, 0x44, 0x75, 0x0b, 0x12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PCIE_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0xd995e954, 0xbbc1, 0x430f, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_FW_ERR_REC_REF_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0x81212a96, 0x09ed, 0x4996, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PCI_X_BUS_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0xc5753963, 0x3b84, 0x4095, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_PCI_DEV_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0xeb5e4685, 0xca66, 0x4769, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_DMAR_GENERIC_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0x5b51fef7, 0xc79d, 0x4434, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8f, 0x1b, 0xaa, 0x62, 0xde, 0x3e, 0x2c, 0x64)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_DMAR_VT_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0x71761d37, 0x32b2, 0x45cd, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xa7, 0xd0, 0xb0, 0xfe, 0xdd, 0x93, 0xe8, 0xcf)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_SEC_DMAR_IOMMU_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0x036f84e1, 0x7f37, 0x428c, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xa7, 0x9e, 0x57, 0x5f, 0xdf, 0xaa, 0x84, 0xec)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Processor Generic Error Section (Table 254)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct cper_proc_generic_error_section {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 validation;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 proc_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 proc_isa;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 error_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 operation;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 flags;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 level;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 reserved;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 cpu_version;</span><br><span style="color: hsl(120, 100%, 40%);">+ char cpu_brand_string[128];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 proc_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 target_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 requestor_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 responder_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 instruction_ip;</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed cper_proc_generic_error_section_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Processor Generic Error Section, Validation Bits field (Table 254) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_PROC_TYPE BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_PROC_ISA BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_PROC_ERR_TYPE BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_OPERATION BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_FLAGS BIT(4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_LEVEL BIT(5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_CPU_VERSION BIT(6)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_CPU_BRAND BIT(7)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_CPU_ID BIT(8) /* LAPIC ID, not CPUID */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_TGT_ADDR BIT(9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_REQR_ID BIT(10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_RSPR_ID BIT(11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_VALID_INSTR_IP BIT(12)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Processor Generic Error Section, Processor Type field (Table 254) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_PROCTYPE_IA32X64 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_PROCTYPE_IA64 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_PROCTYPE_ARM 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Processor Generic Error Section, Processor ISA (@time of fail) (Table 254) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ISA_IA32 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ISA_IA64 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ISA_X64 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ISA_ARM32 0x3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ISA_ARM64 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* error_type definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Processor Generic Error Section, Processor Error Type field (Table 254) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERRTYPE_UNKNOWN 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERRTYPE_CACHE 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERRTYPE_TLB 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERRTYPE_BUS 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERRTYPE_UARCH 0x8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Processor Generic Error Section, Operation field (Table 254) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERROP_UNKNOWN 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERROP_READ 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERROP_WRITE 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_ERROP_EXECUTION 0x3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Processor Generic Error Section, Flags field (Table 254) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_FLAG_RESTARTABLE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_FLAG_PRECISE_IP 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_FLAG_OVERFLOW 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GENPROC_FLAG_CORRECTED 0x3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * IA32/X64 Processor Error Section (Table 255)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct cper_ia32x64_proc_error_section {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 validation;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 apicid;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 cpuid[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PROC_ERR_INFO_NUM x 64-byte structures */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PROC_CONTEXT_INFO_NUM x context structures */</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed cper_ia32x64_proc_error_section_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Processor Error, Validation Bits field (Table 255) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64SEC_VALID_LAPIC BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64SEC_VALID_CPUID BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64SEC_VALID_ERRNUM_SH 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64SEC_VALID_ERRNUM_MAX 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64SEC_VALID_ERRNUM_MASK \</span><br><span style="color: hsl(120, 100%, 40%);">+ (I32X64SEC_VALID_ERRNUM_MAX \</span><br><span style="color: hsl(120, 100%, 40%);">+ << I32X64SEC_VALID_ERRNUM_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64SEC_VALID_CTXNUM_SH 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64SEC_VALID_CTXNUM_MAX 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64SEC_VALID_CTXNUM_MASK \</span><br><span style="color: hsl(120, 100%, 40%);">+ (I32X64SEC_VALID_CTXNUM_MAX \</span><br><span style="color: hsl(120, 100%, 40%);">+ << I32X64SEC_VALID_CTXNUM_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Processor Error Information Structure (Table 256) */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct cper_ia32x64_proc_error_info {</span><br><span style="color: hsl(120, 100%, 40%);">+ guid_t type; /* cache, tlb, bus, micro-architecture specific */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 validation;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 check_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 target_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 requestor_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 responder_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 instruction_ip;</span><br><span style="color: hsl(120, 100%, 40%);">+} cper_ia32x64_proc_error_info_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Processor Error Information Structs, Err Struct Types (Table 256) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROCESSOR_CACHE_CHK_ERROR_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0xa55701f5, 0xe3ef, 0x43de, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xac, 0x72, 0x24, 0x9b, 0x57, 0x3f, 0xad, 0x2c)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROCESSOR_TLB_CHK_ERROR_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0xfc06b535, 0x5e1f, 0x4562, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x9f, 0x25, 0x0a, 0x3b, 0x9a, 0xdb, 0x63, 0xc3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROCESSOR_BUS_CHK_ERROR_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0x1cf3f8b3, 0xc5b1, 0x49a2, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xaa, 0x59, 0x5e, 0xef, 0x92, 0xff, 0xa6, 0x3c)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROCESSOR_MS_CHK_ERROR_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+ GUID_INIT(0x48ab7f57, 0xdc34, 0x4f6c, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xa7, 0xd3, 0xb0, 0xb5, 0xb0, 0xa7, 0x43, 0x14)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum cper_x86_check_type {</span><br><span style="color: hsl(120, 100%, 40%);">+ X86_PROCESSOR_CACHE_CHK, /* X86_PROCESSOR_CACHE_CHK_ERROR_GUID */</span><br><span style="color: hsl(120, 100%, 40%);">+ X86_PROCESSOR_TLB_CHK, /* X86_PROCESSOR_TLB_CHK_ERROR_GUID */</span><br><span style="color: hsl(120, 100%, 40%);">+ X86_PROCESSOR_BUS_CHK, /* X86_PROCESSOR_BUS_CHK_ERROR_GUID */</span><br><span style="color: hsl(120, 100%, 40%);">+ X86_PROCESSOR_MS_CHK /* X86_PROCESSOR_MS_CHK_ERROR_GUID */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Processor Error Information Structure, Validation Bits (Tbl 256) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64ERRINFO_VALID_CHECK BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64ERRINFO_VALID_TGT_ADDR BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64ERRINFO_VALID_RQST_ID BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64ERRINFO_VALID_RSPD_ID BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define I32X64ERRINFO_VALID_IPPTR BIT(4)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Proc. Error Info: Cache/TLB/Check defs (Tables 257, 258, 259) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_XACT_TYPE_VALID BIT(0) /* CACHE|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPERATION_VALID BIT(1) /* CACHE|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_LEVEL_VALID BIT(2) /* CACHE|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_CONTEXT_CORPT_VALID BIT(3) /* CACHE|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_UNCORRECTED_VALID BIT(4) /* CACHE|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_PRECISE_IP_VALID BIT(5) /* CACHE|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_RESTARTABLE_VALID BIT(6) /* CACHE|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OVERFLOW_VALID BIT(7) /* CACHE|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_PART_TYPE_VALID BIT(8) /* | |BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_TIMEOUT_VALID BIT(9) /* | |BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_ADDR_SPACE_VALID BIT(10) /* | |BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_XACT_SH 16 /* CA|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_XACT_MASK (0x3 << X86_PROC_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_XACT_INSTRUCTION (0 << X86_PROC_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_XACT_DATA (1 << X86_PROC_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_XACT_GENERIC (2 << X86_PROC_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_SH 18 /* CA|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_MASK (0xf << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_GENERIC (0 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_GENREAD (1 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_GENWRITE (2 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_DATAREAD (3 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_DATAWRITE (4 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_FETCH (5 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_PREFETCH (6 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CA| | */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_EVICTION (7 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OPER_SNOOP (8 << X86_PROC_CHK_OPER_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_LEVEL_SH 22 /* CA|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_LEVEL_MASK (0x7 << X86_PROC_CHK_LEVEL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_LEVEL_1 (1 << X86_PROC_CHK_LEVEL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_LEVEL_2 (2 << X86_PROC_CHK_LEVEL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_LEVEL_3 (3 << X86_PROC_CHK_LEVEL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_CTX_CORRUPT (1 << 25) /* CA|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_UNCORRECTED (1 << 26) /* CA|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_PRECISE_IP (1 << 27) /* CA|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_RESTARTABLE_IP (1 << 28) /* CA|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OVERFLOW (1 << 29) /* CA|TLB|BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_PARTIC_SH 30 /* | |BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_PARTIC_MASK (3 << X86_PROC_CHK_PARTIC_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_ORIGINATED (0 << X86_PROC_CHK_PARTIC_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_RESPONDED (1 << X86_PROC_CHK_PARTIC_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_OBSERVED (2 << X86_PROC_CHK_PARTIC_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_TIMEOUT 0x100000000 /* BIT(32) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_SPACE_SH 33 /* | |BUS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_SPACE_MASK (0x3 << X86_PROC_CHK_SPACE_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_SPACE_MEM (0 << X86_PROC_CHK_SPACE_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_SPACE_IO (2 << X86_PROC_CHK_SPACE_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_CHK_SPACE_OTHER (3 << X86_PROC_CHK_SPACE_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+/* MS check defines & aligns (Table 260 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_ERROR_TYPE_VALID BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CONTEXT_CORPT_VALID BIT(1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_UNCORRECTED_VALID BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_PRECISE_IP_VALID BIT(3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_RESTARTABLE_IP_VALID BIT(4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_OVERFLOW_VALID BIT(5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_XACT_SH 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_XACT_MASK (0x7 << X86_PROC_MS_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_XACT_TYPE_NOERR (0 << X86_PROC_MS_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_XACT_TYPE_UNCL (1 << X86_PROC_MS_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_XACT_TYPE_UCODE_ROM (2 << X86_PROC_MS_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_XACT_TYPE_EXT (3 << X86_PROC_MS_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_XACT_TYPE_FRC (4 << X86_PROC_MS_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_XACT_TYPE_INT_UNCL (5 << X86_PROC_MS_CHK_XACT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_CTX_CORRUPT (1 << 19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_UNCORRECTED (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_PRECISE_IP (1 << 21)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_RESTARTABLE_IP (1 << 22)</span><br><span style="color: hsl(120, 100%, 40%);">+#define X86_PROC_MS_CHK_OVERFLOW (1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Processor Context Information (Table 261) */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct cper_ia32x64_context {</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 type;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 array_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 msr_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 mmap_addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* N bytes of register array */</span><br><span style="color: hsl(120, 100%, 40%);">+} cper_ia32x64_context_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Processor Context Information, Types field (Table 261) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_IA32X64_CTX_UNCL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_IA32X64_CTX_MSR 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_IA32X64_CTX_32BIT_EX 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_IA32X64_CTX_64BIT_EX 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_IA32X64_CTX_FXSAVE 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_IA32X64_CTX_32BIT_DBG 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_IA32X64_CTX_64BIT_DBG 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define CPER_IA32X64_CTX_MEMMAPPED 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Processor Context IA32 Register State (Table 262) */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct cper_ia32x64_ctx_ia32state {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 eax;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ebx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ecx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 edx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 esi;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 edi;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 ebp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 esp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 cs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 ds;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 ss;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 es;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 fs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 gs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 eflags;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 eip;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cr0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cr1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cr2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cr3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cr4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 gdtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 idtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 ldtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 tr;</span><br><span style="color: hsl(120, 100%, 40%);">+} cper_ia32x64_ctx_ia32state_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* IA32/X64 Processor Context X64 Register state (Table 263) */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct cper_ia32x64_ctx_x64state {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rax;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rbx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rcx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rdx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rsi;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rdi;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rbp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rsp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 r8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 r9;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 r10;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 r11;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 r12;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 r13;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 r14;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 r15;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 cs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 ds;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 ss;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 es;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 fs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 gs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rflags;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 eip;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 cr0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 cr1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 cr2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 cr3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 cr4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 cr8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 gdtr[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 idtr[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 ldtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 tr;</span><br><span style="color: hsl(120, 100%, 40%);">+} cper_ia32x64_ctx_x64state_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline cper_timestamp_t cper_timestamp(int precise)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ cper_timestamp_t ts;</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_RTC)</span><br><span style="color: hsl(120, 100%, 40%);">+ struct rtc_time time;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rtc_get(&time);</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.sec = bin2bcd(time.sec);</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.min = bin2bcd(time.min);</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.hour = bin2bcd(time.hour);</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.day = bin2bcd(time.mday);</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.month = bin2bcd(time.mon);</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.year = bin2bcd(time.year % 100);</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.century = bin2bcd(time.year / 100);</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.precise = precise;</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.sec = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.min = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.hour = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.day = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.month = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.year = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.century = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ts.precise = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ return ts;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Calculate the size of an IA32/X64 context by its type. Some types have a</span><br><span style="color: hsl(120, 100%, 40%);">+ * predetermined size, and others are variable size. All sizes are rounded up</span><br><span style="color: hsl(120, 100%, 40%);">+ * to the nearest multiple of 16 bytes (See Processor Context field of</span><br><span style="color: hsl(120, 100%, 40%);">+ * Table 255).</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * type is one of:</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPER_IA32X64_CTX_UNCL</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPER_IA32X64_CTX_MSR</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPER_IA32X64_CTX_32BIT_EX</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPER_IA32X64_CTX_64BIT_EX</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPER_IA32X64_CTX_FXSAVE</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPER_IA32X64_CTX_32BIT_DBG</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPER_IA32X64_CTX_64BIT_DBG</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPER_IA32X64_CTX_MEMMAPPED</span><br><span style="color: hsl(120, 100%, 40%);">+ * num is the number of items in the context's register array</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static inline size_t cper_ia32x64_ctx_sz_bytype(int type, int arr_num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t sz = sizeof(cper_ia32x64_context_t);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (type) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case CPER_IA32X64_CTX_32BIT_EX:</span><br><span style="color: hsl(120, 100%, 40%);">+ return ALIGN_UP(sz + sizeof(cper_ia32x64_ctx_ia32state_t), 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ case CPER_IA32X64_CTX_64BIT_EX:</span><br><span style="color: hsl(120, 100%, 40%);">+ return ALIGN_UP(sz + sizeof(cper_ia32x64_ctx_x64state_t), 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ case CPER_IA32X64_CTX_UNCL:</span><br><span style="color: hsl(120, 100%, 40%);">+ case CPER_IA32X64_CTX_MSR:</span><br><span style="color: hsl(120, 100%, 40%);">+ case CPER_IA32X64_CTX_FXSAVE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case CPER_IA32X64_CTX_32BIT_DBG:</span><br><span style="color: hsl(120, 100%, 40%);">+ case CPER_IA32X64_CTX_64BIT_DBG:</span><br><span style="color: hsl(120, 100%, 40%);">+ case CPER_IA32X64_CTX_MEMMAPPED:</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Table 261: "size ... is determined by (Array Size / 8)" */</span><br><span style="color: hsl(120, 100%, 40%);">+ return ALIGN_UP(sz + arr_num * 8, 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline size_t cper_ia32x64_check_sz(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return sizeof(cper_ia32x64_proc_error_info_t); /* all the same size */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return PROC_ERR_INFO_NUM for an IA32/X64 Processor Error Record */</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int cper_ia32x64_proc_num_chks(</span><br><span style="color: hsl(120, 100%, 40%);">+ cper_ia32x64_proc_error_section_t *x86err)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ int shift;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = I32X64SEC_VALID_ERRNUM_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ shift = I32X64SEC_VALID_ERRNUM_SH;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (x86err->validation & mask) >> shift;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return PROC_CONTEXT_INFO_NUM for an IA32/X64 Processor Error Record */</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int cper_ia32x64_proc_num_ctxs(</span><br><span style="color: hsl(120, 100%, 40%);">+ cper_ia32x64_proc_error_section_t *x86err)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ int shift;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = I32X64SEC_VALID_CTXNUM_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ shift = I32X64SEC_VALID_CTXNUM_SH;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (x86err->validation & mask) >> shift;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Do PROC_ERR_INFO_NUM++ of an IA32/X64 error section. Caller should ensure</span><br><span style="color: hsl(120, 100%, 40%);">+ * the max is not being exceeded.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void cper_bump_ia32x64_chk_count(</span><br><span style="color: hsl(120, 100%, 40%);">+ cper_ia32x64_proc_error_section_t *x86err)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int count;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ count = cper_ia32x64_proc_num_chks(x86err) + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ x86err->validation &= ~I32X64SEC_VALID_ERRNUM_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ x86err->validation |= count << I32X64SEC_VALID_ERRNUM_SH;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Do PROC_CONTEXT_INFO_NUM++ of an IA32/X64 error section. Caller should</span><br><span style="color: hsl(120, 100%, 40%);">+ * ensure the max is not being exceeded.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void cper_bump_ia32x64_ctx_count(</span><br><span style="color: hsl(120, 100%, 40%);">+ cper_ia32x64_proc_error_section_t *x86err)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int count;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ count = cper_ia32x64_proc_num_ctxs(x86err) + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ x86err->validation &= ~I32X64SEC_VALID_CTXNUM_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ x86err->validation |= count << I32X64SEC_VALID_CTXNUM_SH;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _CPER_H_ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28468">change 28468</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb </div>
<div style="display:none"> Gerrit-Change-Number: 28468 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>