<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28476">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Create an MCA structure<br><br>Convert the Machine Check reporting to use a newly defined structure.<br>This will facilitate later patches that will pass pointers to the MSR<br>values.<br><br>BUG=b:65446699<br>TEST=inspect BERT region, and dmesg, on full patch stack. Use test<br> data plus a failing Grunt system.<br><br>Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/mca.c<br>1 file changed, 26 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28476/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c</span><br><span>index b782ef3..bcaa927 100644</span><br><span>--- a/src/soc/amd/stoneyridge/mca.c</span><br><span>+++ b/src/soc/amd/stoneyridge/mca.c</span><br><span>@@ -20,6 +20,14 @@</span><br><span> #include <soc/northbridge.h></span><br><span> #include <console/console.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct mca_bank {</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t ctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t addr;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t misc;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t cmask;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static const char *const mca_bank_name[] = {</span><br><span> "Load-store unit",</span><br><span> "Instruction fetch unit",</span><br><span>@@ -33,45 +41,46 @@</span><br><span> void check_mca(void)</span><br><span> {</span><br><span> int i;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t cap;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct mca_bank mci;</span><br><span> int num_banks;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(0, 100%, 40%);">- num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ cap = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = cap.lo & MCA_BANKS_MASK;</span><br><span> </span><br><span> if (is_warm_reset()) {</span><br><span> for (i = 0 ; i < num_banks ; i++) {</span><br><span> if (i == 3) /* Reserved in Family 15h */</span><br><span> continue;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC0_STATUS + (i * 4));</span><br><span style="color: hsl(0, 100%, 40%);">- if (msr.hi || msr.lo) {</span><br><span style="color: hsl(120, 100%, 40%);">+ mci.sts = rdmsr(MC0_STATUS + (i * 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mci.sts.hi || mci.sts.lo) {</span><br><span> int core = cpuid_ebx(1) >> 24;</span><br><span> </span><br><span> printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n",</span><br><span> core, i, mca_bank_name[i]);</span><br><span> </span><br><span> printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- i, msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC0_ADDR + (i * 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ i, mci.sts.hi, mci.sts.lo);</span><br><span style="color: hsl(120, 100%, 40%);">+ mci.addr = rdmsr(MC0_ADDR + (i * 4));</span><br><span> printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- i, msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC0_MISC + (i * 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ i, mci.addr.hi, mci.addr.lo);</span><br><span style="color: hsl(120, 100%, 40%);">+ mci.misc = rdmsr(MC0_MISC + (i * 4));</span><br><span> printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- i, msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC0_CTL + (i * 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ i, mci.misc.hi, mci.misc.lo);</span><br><span style="color: hsl(120, 100%, 40%);">+ mci.ctl = rdmsr(MC0_CTL + (i * 4));</span><br><span> printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- i, msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC0_CTL_MASK + i);</span><br><span style="color: hsl(120, 100%, 40%);">+ i, mci.ctl.hi, mci.ctl.lo);</span><br><span style="color: hsl(120, 100%, 40%);">+ mci.cmask = rdmsr(MC0_CTL_MASK + i);</span><br><span> printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- i, msr.hi, msr.lo);</span><br><span style="color: hsl(120, 100%, 40%);">+ i, mci.cmask.hi, mci.cmask.lo);</span><br><span> }</span><br><span> }</span><br><span> }</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ mci.sts.lo = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ mci.sts.hi = 0;</span><br><span> for (i = 0 ; i < num_banks ; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), mci.sts);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28476">change 28476</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28476"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff </div>
<div style="display:none"> Gerrit-Change-Number: 28476 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>