<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28473">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/fam15: Add more MCA information<br><br>Add more definitions to be used for Machine Check Architecture<br>support, mainly for determining the type of error that is being<br>interpreted. MCA is described in detail in the BKDG.<br><br>BUG=b:65446699<br>TEST=inspect BERT region, and dmesg, on full patch stack. Use test<br> data plus a failing Grunt system.<br><br>Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/include/cpu/amd/amdfam15.h<br>1 file changed, 162 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28473/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h</span><br><span>index 1441c05..bafd2b8 100644</span><br><span>--- a/src/include/cpu/amd/amdfam15.h</span><br><span>+++ b/src/include/cpu/amd/amdfam15.h</span><br><span>@@ -16,13 +16,175 @@</span><br><span> #ifndef CPU_AMD_FAM15_H</span><br><span> #define CPU_AMD_FAM15_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define MCG_CAP 0x00000179</span><br><span> # define MCA_BANKS_MASK 0xff</span><br><span> #define MC0_CTL 0x00000400</span><br><span> #define MC0_STATUS 0x00000401</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_VAL BIT(63 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_OVERFLOW BIT(62 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_UC BIT(61 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_EN BIT(60 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_MISCV BIT(59 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_ADDRV BIT(58 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_PCC BIT(57 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_COREID_VAL BIT(56 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_CECC BIT(46 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_UECC BIT(45 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_DEFERRED BIT(44 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_POISON BIT(43 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_SUBLINK BIT(41 - 32)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_LO_ERRCODE_EXT_SH 16</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)</span><br><span> #define MC0_ADDR 0x00000402</span><br><span> #define MC0_MISC 0x00000403</span><br><span> #define MC0_CTL_MASK 0xC0010044</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Helpers for interpreting MC[i]_STATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_valid(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_over(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_uc(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_UC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_en(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_miscv(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_MISCV);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_addrv(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_ADDRV);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_pcc(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_PCC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_idv(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_cecc(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_CECC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_uecc(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_UECC);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_defd(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_DEFERRED);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_poison(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_POISON);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int mca_sublink(msr_t msr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(msr.hi & MCA_STATUS_HI_SUBLINK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline uint16_t mca_err_code(msr_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return reg.lo &= MCA_STATUS_LO_ERRCODE_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline uint16_t mca_err_extcode(msr_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return reg.lo &= MCA_STATUS_LO_ERRCODE_EXT_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TLB Errors 0000 0000 0001 TTLL */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_DETECT 0xfff0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory Errors 0000 0001 RRRR TTLL */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_DETECT 0xff00</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bus Errors 0000 1PPT RRRR IILL */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_DETECT 0xf800</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Int. Unclassified Errors 0000 01UU 0000 0000 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_INT_DETECT 0xfc00</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_LS 0 /* Load-store, including DC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_IF 1 /* Instruction Fetch, including IC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_CU 2 /* Combined Unit, including L2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* bank 3 reserved */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_NB 4 /* Northbridge, including IO link */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_EX 5 /* Execution Unit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCA_BANK_FP 6 /* Floating Point */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum mca_err_code_types {</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_UNKNOWN,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_TLB,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_MEM,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_BUS,</span><br><span style="color: hsl(120, 100%, 40%);">+ MCA_ERRTYPE_INT</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline enum mca_err_code_types mca_err_type(msr_t reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t error = mca_err_code(reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_BUS;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (error & MCA_ERRCODE_INT_DETECT)</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_INT;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (error & MCA_ERRCODE_MEM_DETECT)</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_MEM;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (error & MCA_ERRCODE_TLB_DETECT)</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_TLB;</span><br><span style="color: hsl(120, 100%, 40%);">+ return MCA_ERRTYPE_UNKNOWN;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define MSR_SMM_BASE 0xC0010111</span><br><span> #define MSR_TSEG_BASE 0xC0010112</span><br><span> #define MSR_SMM_MASK 0xC0010113</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28473">change 28473</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68 </div>
<div style="display:none"> Gerrit-Change-Number: 28473 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>