<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28437">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek/mt8183: Add MediaTek DDR driver<br><br>Add DDR driver to initialize memory.<br><br>BUG=b:80501386<br>BRANCH=none<br>TEST=Boots correctly on Kukui, and inits DRAM successfully with related<br> patches.<br><br>Change-Id: Iaaa1db170c168a58b020095ae45d98355d8dfcb0<br>Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com><br>---<br>M src/soc/mediatek/mt8183/Kconfig<br>M src/soc/mediatek/mt8183/Makefile.inc<br>A src/soc/mediatek/mt8183/dramc_pi_basic_api.c<br>A src/soc/mediatek/mt8183/dramc_pi_calibration_api.c<br>M src/soc/mediatek/mt8183/emi.c<br>M src/soc/mediatek/mt8183/include/soc/addressmap.h<br>A src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h<br>A src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h<br>A src/soc/mediatek/mt8183/include/soc/dramc_register.h<br>M src/soc/mediatek/mt8183/include/soc/emi.h<br>M src/soc/mediatek/mt8183/include/soc/memlayout.ld<br>A src/soc/mediatek/mt8183/memory.c<br>M src/soc/mediatek/mt8183/pll.c<br>13 files changed, 6,648 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28437/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig</span><br><span>index b58be7f..1c78b18 100644</span><br><span>--- a/src/soc/mediatek/mt8183/Kconfig</span><br><span>+++ b/src/soc/mediatek/mt8183/Kconfig</span><br><span>@@ -19,4 +19,14 @@</span><br><span> select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span> select VBOOT_SEPARATE_VERSTAGE</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DEBUG_DRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Output verbose DRAM related debug message"</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option enables additional DRAM related debug messages.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MEMORY_TEST</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>index 8fece79..2c128f9 100644</span><br><span>--- a/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>+++ b/src/soc/mediatek/mt8183/Makefile.inc</span><br><span>@@ -21,6 +21,10 @@</span><br><span> verstage-y += ../common/wdt.c</span><br><span> </span><br><span> romstage-y += ../common/cbmem.c emi.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += dramc_pi_basic_api.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += dramc_pi_calibration_api.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memory.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c</span><br><span> romstage-y += ../common/gpio.c gpio.c</span><br><span> romstage-y += ../common/mmu_operations.c mmu_operations.c</span><br><span> romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c</span><br><span>diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c</span><br><span>new file mode 100644</span><br><span>index 0000000..6619540</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c</span><br><span>@@ -0,0 +1,1852 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/infracfg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/spm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pll.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_register.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_pi_api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_broadcast_onoff(u32 bOnOff)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&mt8183_infracfg->dramc_wbr, bOnOff);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 get_dramc_broadcast(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return read32(&mt8183_infracfg->dramc_wbr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void transfer_pll_to_spm_control(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 shu_level;</span><br><span style="color: hsl(120, 100%, 40%);">+ shu_level = read32(&ch[0].ao.shustatus);</span><br><span style="color: hsl(120, 100%, 40%);">+ shu_level = (shu_level & 0x00000006) >> 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set SPM project code and enable clock enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mtk_spm->poweron_config_set,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 16) | (0x1 << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xb16 << 16) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set SPM pinmux */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xffffffff << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xffffffff << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_spm->spm_power_on_val0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 8) | (0xf << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_spm->spm_s1_mode_ch, (0x3 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ shu_level = (shu_level == 1) ? 2 : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mtk_spm->spm_power_on_val0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 28), (shu_level << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&mtk_spm->dramc_dpy_clk_sw_con2,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 2), (shu_level << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = CHANNEL_A; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.pll1, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.pll2, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_hw_dqs_gating_tracking(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.stbcal,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 26) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 16) | (0x1 << 8) | (0x1 << 6),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 16) | (0x1 << 8) | (0x0 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.misc_ctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 24) | (0x1f << 11) | (0xf << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 24) | (0x0 << 11) | (0x0 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dq[6], (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dq[6], (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_cmd[6], (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_hw_gating_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.stbcal,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.stbcal,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 20) | (0x3 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_hw_dqs_gating_tracking(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_input_delay_tracking_init(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable RX_FIFO macro DIV4 clock CG */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl1, 0xffffffff);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DVS mode to RG mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[0].b[0].rxdvs[2], (0x3 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[0].b[1].rxdvs[2], (0x3 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[1].b[0].rxdvs[2], (0x3 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[1].b[1].rxdvs[2], (0x3 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* tracking rising and update rising/falling together */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[0].b[b].rxdvs[2], (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[2], (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQS, DQ, DQM (DQ, DQM are tied together now)</span><br><span style="color: hsl(120, 100%, 40%);">+ * -> controlled using DQM MAX_MIN */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.r[0].b[b].rxdvs[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 0) | (0x3f << 8) | (0x0 << 16) | (0x7f << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.r[0].b[b].rxdvs[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 16) | (0xffff << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 16) | (0x2 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQ/DQS Rx DLY adjustment for tracking mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[0].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 26) | (0x3 << 24) | (0x3 << 18) | (0x3 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQS, DQ, DQM (DQ, DQM are tied together now)</span><br><span style="color: hsl(120, 100%, 40%);">+ * -> controlled using DQM MAX_MIN */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 0) | (0x3f << 8) | (0x0 << 16) | (0x7f << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 16) | (0xffff << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 16) | (0x2 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQ/DQS Rx DLY adjustment for tracking mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 26) | (0x3 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 18) | (0x3 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_input_delay_tracking(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_cmd[10],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 28) | (0x7 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rx DLY tracking setting (Static) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 29) | (0xf << 4) | (0x1 << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 29) | (0x0 << 4) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 29) | (0xf << 4) | (0x1 << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 29) | (0x0 << 4) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[b].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 28) | (0x7 << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 28) | (0x0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[b].dq[5], (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 rank = RANK_0; rank < RANK_MAX; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rx DLY tracking update enable (HW mode) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.r[rank].b[0].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 30) | (0x1 << 28) | (0x1 << 23),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 30) | (0x1 << 28) | (0x1 << 23));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.r[rank].b[1].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 30) | (0x1 << 28) | (0x1 << 23),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 30) | (0x1 << 28) | (0x1 << 23));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_impedance_tracking_enable(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_ctrl0, (0x1 << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 26) | (0x1 << 17) | (0x7 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.impcal, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl0, (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.impcal, (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.impcal, (0x1 << 14));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[1].ao.refctrl0, (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 3));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_runtime_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn = 0, shu = 0, shuCnt = DRAM_DFS_SHUFFLE_MAX;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.refctrl0, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[1].ao.refctrl0, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ transfer_pll_to_spm_control();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_spm->spm_power_on_val0, (0x3 << 25));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("TX_TRACKING: OFF\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_input_delay_tracking_init(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_input_delay_tracking(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("RX_TRACKING: ON\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_hw_gating_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_hw_gating_onoff(CHANNEL_A, GATING_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("HW_GATING: ON\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.stbcal2,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 4) | (0x3 << 8) | (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("HW_GATING DBG: OFF\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ZQCS_ENABLE_LP4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[1].ao.spcmdctrl, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("ZQCS_ENABLE_LP4: OFF\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_dramc_phy_dcm(0);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("LOWPOWER_GOLDEN_SETTINGS(DCM): OFF\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < shuCnt; shu++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 1) | (0x3 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("DUMMY_READ_FOR_DQS_GATING_RETRY: OFF\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].phy.misc_spm_ctrl0, 0xfbffefff);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[1].phy.misc_spm_ctrl0, 0xfbffefff);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].phy.misc_spm_ctrl2, 0xffffffef);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[1].phy.misc_spm_ctrl2, 0x7fffffef);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("SPM_CONTROL_AFTERK: ON\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_impedance_tracking_enable();</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("IMPEDANCE_TRACKING: ON\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmdctrl, (0x3 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.hw_mrr_fun,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("TEMP_SENSOR: ON\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.refctrl0, (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("PER_BANK_REFRESH: OFF\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.dvfs_emi_clk, (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dvfsdll, (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void cke_fix_onoff(int option, u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 on, off;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* if CKE is dynamic, set both CKE fix On and Off as 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (option == CKE_DYNAMIC) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* After CKE FIX on/off,</span><br><span style="color: hsl(120, 100%, 40%);">+ * CKE should be returned to dynamic (control by HW) */</span><br><span style="color: hsl(120, 100%, 40%);">+ on = off = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* if CKE fix on is set as 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ * CKE fix off should also be set as 0; vice versa */</span><br><span style="color: hsl(120, 100%, 40%);">+ on = option;</span><br><span style="color: hsl(120, 100%, 40%);">+ off = (1 - option);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.ckectrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void auto_refresh_cke_off(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 broadcast_bak = get_dramc_broadcast();</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(3);</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_FIXOFF, CHANNEL_A);</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_FIXOFF, CHANNEL_B);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(broadcast_bak);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_set_rank_engine2(u8 chn, u8 u1RankSel)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dramctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << DRAMCTRL_ADRDECEN_TARKMODE_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRKSEL_MASK);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRK_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (u1RankSel << TEST2_4_TESTAGENTRK_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void save_restore_dummyrd(u8 chn, u8 type)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static u32 uiReg0D0h = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (type == SAVE_VALUE)</span><br><span style="color: hsl(120, 100%, 40%);">+ uiReg0D0h = read32(&ch[chn].ao.dummy_rd);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.dummy_rd, uiReg0D0h);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void save_restore_multi_reg(u8 type, u32 **reg_addr, u32 reg_count)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static u32 u4gpRegBackupVlaue[MAX_BACKUP_REG_CNT];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (reg_count > MAX_BACKUP_REG_CNT) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("save restore count over %d\n", MAX_BACKUP_REG_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (type == SAVE_VALUE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < reg_count; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ u4gpRegBackupVlaue[i] = read32(reg_addr[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < reg_count; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(reg_addr[i], u4gpRegBackupVlaue[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_engine2_init(u8 chn, u8 u1RankSel, u32 test2_1, u32 test2_2,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 testaudpat, u8 log2loopcount)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_rank_engine2(chn, u1RankSel);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_restore_dummyrd(chn, SAVE_VALUE);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.dummy_rd,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DQSG_DMYRD_EN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DQSG_DMYWR_EN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DUMMY_RD_EN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_SREF_DMYRD_EN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DMY_RD_DBG_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << DUMMY_RD_DMY_WR_DBG_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].nao.testchip_dma1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_0_PAT0_MASK | TEST2_0_PAT1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (((test2_1 >> 24) & 0xff) << TEST2_0_PAT0_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (((test2_2 >> 24) & 0xff) << TEST2_0_PAT1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.test2_1, (test2_1 << 4) & 0x00ffffff);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.test2_2, (test2_2 << 4) & 0x00ffffff);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (testaudpat == TEST_XTALK_PATTERN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDMODE_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDBITINV_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTSSOPAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TESTXTALKPAT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.perfctl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << PERFCTL0_RWOFOEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TESTAUDPAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TESTCNT_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ log2loopcount << TEST2_3_TESTCNT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (testaudpat == TEST_AUDIO_PATTERN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINIT_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINC_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTXTALKPAT_SHIFT),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x00000011 << TEST2_4_TESTAUDINIT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0000000d << TEST2_4_TESTAUDINC_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDMODE_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDBITINV_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3, TEST2_3_TESTCNT_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TESTAUDPAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (log2loopcount << TEST2_3_TESTCNT_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TESTAUDPAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TESTCNT_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (log2loopcount << TEST2_3_TESTCNT_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTXTALKPAT_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_engine2_check_complete(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4loop_count = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ while ((read32(&ch[chn].nao.testrpt) &</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TESTRPT_DM_CMP_CPT_RK0_SHIFT)) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ u4loop_count++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("MEASURE_A timeout\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 dramc_engine2_run(u8 chn, enum dram_te_op wr, u8 testaudpat)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4result = 0xffffffff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (wr == TE_OP_READ_CHECK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((testaudpat == TEST_AUDIO_PATTERN) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ (testaudpat == TEST_XTALK_PATTERN))</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDMODE_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (wr == TE_OP_WRITE_READ_CHECK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST1_SHIFT),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_check_complete(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* do Read test */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST1_SHIFT),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_check_complete(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ u4result = read32(&ch[chn].nao.cmp_err);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2W_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST2R_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_3_TEST1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return u4result;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_engine2_end(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4, (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_restore_dummyrd(chn, RESTORE_VALUE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void ddr_phy_pll_setting(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1CAP_SEL;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MID_FINE_TUNE_SEL;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1VTH_SEL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u1VTH_SEL = 0x2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u1CAP_SEL = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u1MID_FINE_TUNE_SEL = 0x2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xFFFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xFFFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (chn == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_shu_opt, 0x1 << 18);</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (chn == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_shu_opt, 0x2 << 18);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.ckmux_sel,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x3 << 18 | 0x3 << 16, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x3 << 18, 0x1 << 18);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x0 << 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (chn == DLL_MASTER_CH) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 31 | 0x1 << 30 | 0xf << 20 | 0xf << 16 |</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xf << 12 | 0x1 << 10 | 0x1 << 9 | 0x1 << 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0 << 31 | 0x0 << 30 | 0x6 << 20 | 0x9 << 16 |</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8 << 12 | 0x1 << 10 | 0x1 << 9 | 0x1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 2 | 0x1 << 0, 0x1 << 2 | 0x0 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 7, 0x1 << 7);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 31 | 0x1 << 30 | 0xf << 20 | 0xf << 16 |</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xf << 12 | 0x1 << 10 | 0x1 << 9 | 0x1 << 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 31 | 0x1 << 30 | 0x7 << 20 | 0x7 << 16 |</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8 << 12 | 0x1 << 10 | 0x1 << 9 | 0x0 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 2 | 0x1 << 0, 0x0 << 2 | 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 7, 0x0 << 7);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *u4RegBackup[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].phy.b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].phy.b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].phy.ca_cmd[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_restore_multi_reg(SAVE_VALUE,</span><br><span style="color: hsl(120, 100%, 40%);">+ u4RegBackup, ARRAY_SIZE(u4RegBackup));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[b].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ca_cmd[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 26M */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, (0x3<<4), 0x0 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MID FINE_TUNE */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1<<26)|(0x1<<27));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1<<26)|(0x1<<27));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1<<26)|(0x1<<27));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.pll4, (0x1<<16)|(0x1<<22));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PLL */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.pll1, (0x1<<31));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.pll2, (0x1<<31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DLL */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], (0x0<<0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x0<<0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], (0x0<<0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<10) | (0x1<<11) | (0x1<<13) | (0x1<<14) | (0x1<<15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<17) | (0x1<<19) | (0x1<<27) | (0x1<<31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<10) | (0x1<<11) | (0x1<<13) | (0x1<<14) | (0x1<<15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<17) | (0x1<<19) | (0x1<<27) | (0x1<<31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<10) | (0x1<<11) | (0x1<<13) | (0x1<<15) | (0x1<<16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<17) | (0x1<<19) | (0x1<<27) | (0x1<<31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* RESETB */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], (0x1<<3));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], (0x1<<3));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], (0x1<<3));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MPLL 52M */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].pll[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7<<0)|(0x3<<18), (0x0<<0)|(0x1<<18));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].pll[10],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7<<0)|(0x3<<18), (0x0<<0)|(0x1<<18));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].pll[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff<<16) | 0x1 << 0, (0x7b00<<16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].pll[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff<<16) | 0x1 << 0, (0x7b00<<16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], (0x1<<1));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], (0x1<<1));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], (0x1<<1));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], (0x1<<11));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], (0x1<<19));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], (0x1<<19));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3<<22) | (0x3<<24) | (0x3<<28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (u1MID_FINE_TUNE_SEL<<22) | (u1VTH_SEL<<24) | (u1CAP_SEL<<28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3<<22) | (0x3<<24) | (0x3<<28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (u1MID_FINE_TUNE_SEL<<22)|(u1VTH_SEL<<24) | (u1CAP_SEL<<28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3<<22) | (0x3<<24) | (0x3<<28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (u1MID_FINE_TUNE_SEL<<22) | (u1VTH_SEL<<24) | (u1CAP_SEL<<28));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* RESETB */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], (0x1<<3));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], (0x1<<3));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], (0x1<<3));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PLL EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.pll1, (0x1<<31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.pll2, (0x1<<31));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MID FINE_TUNE Init 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.pll4, (0x1<<16)|(0x1<<22));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MID FINE_TUNE Init 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<26) | (0x1<<27), (0x1<<26) | (0x0<<27));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<26) | (0x1<<27), (0x1<<26) | (0x0<<27));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<26) | (0x1<<27), (0x1<<26) | (0x0<<27));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (chn == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<13) | (0x1<<15) | (0x1<<16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<17) | (0x1<<19),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<13) | (0x1<<15) | (0x1<<16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<17) | (0x1<<19));</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (chn == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<13) | (0x1<<15) | (0x1<<16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<17) | (0x1<<19),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<13) | (0x1<<15) | (0x1<<16) | (0x1<<17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<11) | (0x1<<13) | (0x1<<14) | (0x1<<15) | (0x1<<17));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1<<11) | (0x1<<13) | (0x1<<14) | (0x1<<15) | (0x1<<17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 10) | (0x1 << 13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 15) | (0x1 << 16) | (0x1 << 17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 19) | (0x1 << 27) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 10) | (0x1 << 13) | (0x1 << 14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 15) | (0x1 << 17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 19) | (0x1 << 27) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 10) | (0x1 << 13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 14) | (0x1 << 15) | (0x1 << 17) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 19) | (0x1 << 27) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_cg_ctrl0, (0x1 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DLL */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_restore_multi_reg(RESTORE_VALUE,</span><br><span style="color: hsl(120, 100%, 40%);">+ u4RegBackup, ARRAY_SIZE(u4RegBackup));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_DYNAMIC, CHANNEL_A);</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_DYNAMIC, CHANNEL_B);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[0].pll[5], (0x1<<0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[0].pll[7], (0x1<<0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[0].pll[14], (0x1<<1));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[0].pll20, (0x1<<1));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].pll[14],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff<<16), 0x0208 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].pll20,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff<<16), 0x0208 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].pll[15],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffffffff<<0), 0xC03 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].pll21,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffffffff<<0), 0xC03 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void update_initial_settings(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 u2RXVrefDefault = 0x8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t r = 0; r < 2; r++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 23) | (0x1 << 28) | (0x3 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].ca_cmd[7], (0xf << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[3], (0x1 << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[10], (0x1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5) | (0x1 << 6) | (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5) | (0x1 << 6) | (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.b[0].dq[3], (0x1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.b[1].dq[3], (0x1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dq[5], (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dq[5], (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[5], (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5) | (0x1 << 6),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5) | (0x0 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dq[6], (0x1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dq[6], (0x1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[0].dq[6], (0x3 << 0), (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[1].dq[6], (0x1 << 0), (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_cmd[6], (0x3 << 0), (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dq[6], (0x1 << 3));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dq[6], (0x1 << 3));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 3));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dq[6], (0x1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dq[6], (0x1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u2RXVrefDefault = 0xE;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0), (u2RXVrefDefault << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[b].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 8), (u2RXVrefDefault << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dq[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dq[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ca_cmd[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_gating_mode(chn, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[8], (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.ca_cmd[8], (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].misc, (0xf << 0), (0x2 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2a << 20) | (0x1 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].b[0].dq[5], (0x3f << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].b[1].dq[5], (0x3f << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], (0x3f << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x3f << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], (0x3f << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], (0x3f << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IMP Tracking Init Settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].impcal1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 17) | (0xff << 20) | (0xf << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x4 << 0) | (0x4 << 17) | (0x10 << 20) | (0x8 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.srefctrl, (0xf << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.pre_tdqsck[0], (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[0].misc, (0xf << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 0) | (0x1 << 15) | (0x3ff << 22),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 0) | (0x1 << 15) | (0x3ff << 22),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 0) | (0x1 << 15) | (0x3ff << 22),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_ctrl3, (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 8) | (0x1 << 12) | (0x1 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 8) | (0x1 << 12) | (0x1 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.clkar,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 0) | (0x1 << 15),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7fff << 0) | (0x1 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.write_lev, (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dummy_rd, (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.eyescan,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 8) | (0x1 << 9) | (0x1 << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[0].dll[0], (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[1].dll[0], (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], (0x1 << 21));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.perfctl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 15) | (0x1 << 19) | (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.srefctrl, (0x1 << 22));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shuctrl1, (0xff << 0), (0x1a << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 7) | (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 7) | (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.stbcal2, (0x1 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable RODT tracking */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].rodtenstb, (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Rx Gating tracking settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].dqsg,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 11) | (0xf << 12),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 11) | (0x9 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqscal,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 7) | (0x1 << 15),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 7) | (0x0 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqscal,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 7) | (0x1 << 15),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 7) | (0x0 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].stbcal,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 4) | (0x1 << 8),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x1 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[0].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 8), (0x4 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[1].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 8), (0x4 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.ca_cmd[10], (0xff << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[0].dq[8], (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[1].dq[8], (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable WDQS */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[0].dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 16) | (0x1 << 17),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 16) | (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[1].dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 16) | (0x1 << 17),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 16) | (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[0].odtctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 30) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.drsctrl, (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.refctrl0, (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.zqcs, (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dummy_rd, (0x3 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shuctrl3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 24), (0xb << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_ctrl3, (0x1 << 27));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dll_fine_tune[1], (0x3 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dll_fine_tune[1], (0x3 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], (0x1 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.misc_ctrl0, (0x1 << 27));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_rxdvs[2], (0x1 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.clkctrl, (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.refctrl1, (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shuctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 2) | (0x3 << 6) | (0x3 << 26),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 2) | (0x3 << 6) | (0x3 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.stbcal2, (0xf << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.pre_tdqsck[0], (0x3 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.ckectrl, (0x1 << 22));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_tx_mck,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 31) | (0x1f << 21) | (0x1f << 26),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 31) | (0xa << 21) | (0xa << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MP setting should set CKECTRL_CKELCKFIX as 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.ckectrl, (0x1 << 23));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Gating error problem happened in M17</span><br><span style="color: hsl(120, 100%, 40%);">+ * has been solved by setting this RG as 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].rodtenstb, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_power_on_sequence(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* reset dram = low */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CKE low */</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_FIXOFF, CHANNEL_A);</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_FIXOFF, CHANNEL_B);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* delay tINIT1=200us(min) & tINIT2=10ns(min)*/</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(200);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable HW MIOCK control to make CLK always on */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dramc_pd_ctrl, (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(2000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CKE high */</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_FIXON, CHANNEL_A);</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_FIXON, CHANNEL_B);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(2);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("APPLY_LP4_POWER_INIT_SEQUENCE\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void ddr_phy_reserved_rg_setting(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* fine tune */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xFFFF << 6), (0x3 << 6) | (0x4 << 8) | (0x3 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[1].phy.shu[0].ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xFFFF << 6), (0x1 << 6) | (0x4 << 8) | (0x3 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 9) | (0x1f << 16) | (0x7ff << 21),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 8) | (0x7 << 13) | (0x4 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 11) | (0x7 << 19),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 6) | (0x1 << 10) | (0x3 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TX */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 8) | (0x3 << 11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 14) | (0x3fff << 18),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 10) | (0x1 << 13) | (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_duty_set_clk_delay(u8 chn, s8 clkDelay)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t rank;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 delay, delayb, revb0, revb1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ delay = (clkDelay < 0) ? -clkDelay : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ delayb = (clkDelay < 0) ? 0 : clkDelay;</span><br><span style="color: hsl(120, 100%, 40%);">+ revb0 = (delay) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ revb1 = (delayb) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < RANK_MAX; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 24) | (0xf << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (delay << 24) | (delay << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 24) | (0xf << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (delayb << 24) | (delayb << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 8), (revb0 << 8) | (revb1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_duty_set_dqs_delay(u8 chn, s8 dqsDelay)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t rank, dqs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 delay, delayb, revb0, revb1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ delay = (dqsDelay < 0) ? -dqsDelay : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ delayb = (dqsDelay < 0) ? 0 : dqsDelay;</span><br><span style="color: hsl(120, 100%, 40%);">+ revb0 = (delay) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ revb1 = (delayb) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < RANK_MAX; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].phy.shu[0].rk[rank].b[dqs].dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 24) | (0xf << 28) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 16) | (0xf << 20),</span><br><span style="color: hsl(120, 100%, 40%);">+ (delay << 24) | (delay << 28) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (delayb << 16) | (delayb << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 8), (revb0 << 8) | (revb1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_duty_calibration(u8 chn, s8 clkDelay, s8 dqsDelay)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_duty_set_clk_delay(chn, clkDelay);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_duty_set_dqs_delay(chn, dqsDelay);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_mode_reg_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {{0x5d, 0x5d}, {0x5d, 0x5d} },</span><br><span style="color: hsl(120, 100%, 40%);">+ {{0x5d, 0x5d}, {0x5d, 0x5d} },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR14Value_06VDDQ[CHANNEL_NUM][RANK_MAX][FSP_MAX] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {{0x5d, 0x10}, {0x5d, 0x10} },</span><br><span style="color: hsl(120, 100%, 40%);">+ {{0x5d, 0x10}, {0x5d, 0x10} },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn, rank;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 broadcast_bak = get_dramc_broadcast();</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_power_on_sequence();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fix nWR value to 30 (MR01[6:4] = 101B) for DDR3200</span><br><span style="color: hsl(120, 100%, 40%);">+ * Other vendors: Use default MR01 for each FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Set in vInitGlobalVariablesByCondition() )</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR2Value[FSP_MAX] = { 0x0b, 0x2d};</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR13Value_t = 0xc0 | (MR13_RRO << 4) | (1 << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR01Value[FSP_MAX] = { 0x56, 0x56};</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR11Value[FSP_MAX] = { 0x0, 0x23};</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR13Value[FSP_MAX] = { 0x0 | (MR13_RRO << 4) | (1 << 3),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x40 | (MR13_RRO << 4) | (1 << 3)};</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR22Value[FSP_MAX] = {0x38, 0x34};</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < 2; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("%s CH%u RK%u\n", __func__, chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 24), (rank << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ZQ calobration should be done before CBT calibration</span><br><span style="color: hsl(120, 100%, 40%);">+ * by switching to low frequency */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_zq_calibration(chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (uint32_t fsp = FSP_0; fsp < FSP_MAX; fsp++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("chn:%d,rank:%d,fsp%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ chn, rank, fsp);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xd, u1MR13Value[fsp]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MR12 use previous value</span><br><span style="color: hsl(120, 100%, 40%);">+ * MR12 VREF-CA */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc, u1MR12Value[chn][rank][fsp]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1, u1MR01Value[fsp]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x2, u1MR2Value[fsp]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xb, u1MR11Value[fsp]); /* ODT */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SOC-ODT, ODTE-CK, ODTE-CS, Disable ODTD-CA */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x16, u1MR22Value[fsp]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MR14 use previous value</span><br><span style="color: hsl(120, 100%, 40%);">+ * MR14 VREF-DQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn, 0xe,</span><br><span style="color: hsl(120, 100%, 40%);">+ u1MR14Value_06VDDQ[chn][rank][fsp]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MR3 set write-DBI and read-DBI */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1MR03Value = 0x30;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn, 0x3, u1MR03Value);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FSP-1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u1MR13Value_t = 0xc0 | (MR13_RRO<<4) | (1<<3);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, RANK_0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xd, u1MR13Value_t);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, RANK_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xd, u1MR13Value_t);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr13,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1fff << 0) | (0xff << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (13 << 0) | ((u1MR13Value_t | 0x1 << 3) << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].hwset_vrcg,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1fff << 0) | (0xff << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (13 << 0) | ((u1MR13Value_t | (0x1 << 3)) << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr2,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1fff << 0) | (0xff << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (2 << 0) | (u1MR2Value[FSP_1] << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.mrs, (0x3 << 24), (RANK_0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[1].ao.mrs, (0x3 << 24), (RANK_0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(broadcast_bak);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 get_cbt_mode(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return params->cbt_mode_extern;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_setting(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ auto_refresh_cke_off();</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* before switch clock from 26M to PHY, need to init PHY clock first</span><br><span style="color: hsl(120, 100%, 40%);">+ * move CKMUX_SEL_R_PHYCTRLMUX to here (it was originally between</span><br><span style="color: hsl(120, 100%, 40%);">+ * MISC_CG_CTRL0_CLK_MEM_SEL and MISC_CTRL0_R_DMRDSEL_DIV2_OPT)</span><br><span style="color: hsl(120, 100%, 40%);">+ * PHYCTRLDCM 1: follow DDRPHY_conf DCM settings,</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0: follow infra DCM settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.ckmux_sel,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_cg_ctrl0, (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 26M */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.misc_cg_ctrl0, (0x3 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.misc_ctrl0, (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LP4_3200_initial_setting_shu1 begin */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.misc_spm_ctrl1, (0x0000000f << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].phy.misc_spm_ctrl2, ~(0xffffffff << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].phy.misc_spm_ctrl0, ~(0xffffffff << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].phy.misc_cg_ctrl2, 0x6003bf);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].phy.misc_cg_ctrl4, 0x333f3f00);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].pll[1], (0x1 << 4)|(0x7 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0), (0x10 << 0)); /* combine */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x0f << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].pll[4],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 18) | (0x3 << 24) | (0x3 << 26),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 18) | (0x1 << 24) | (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].pll[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 18) | (0x3 << 24) | (0x3 << 26),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 18) | (0x1 << 24) | (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].pll[14], (0x1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].pll20, (0x1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.b[b].dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 16) | (0x3 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[b].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 28), (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.ca_cmd[10], (0x7 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b0_rxdvs[0], (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b1_rxdvs[0], (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b0_rxdvs[0], (0x1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b1_rxdvs[0], (0x1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t r = 0; r < 2; r++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 20), (0x3 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t r = 0; r < 2; r++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 0) | (0xffff << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 0) | (0x2 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 23) | (0x1 << 28) | (0x3 << 30),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 23) | (0x1 << 28) | (0x2 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.b0_rxdvs[0], (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.b1_rxdvs[0], (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t r = 0; r < 2; r++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 8) | (0x3f << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 8) | (0x1f << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[b].dq[4],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7f << 0) | (0x7f << 8),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x10 << 0) | (0x10 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[b].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 0) | (0x3f << 8) | (0x1 << 16) | (0xf << 20) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x10 << 0) | (0xe << 8) | (0x1 << 16) | (0x1 << 20) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[b].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x1 << 7) | (0x1 << 12) | (0x3 << 14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 16) | (0x1 << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 4) | (0x1 << 7) | (0x1 << 12) | (0x0 << 14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 16) | (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[b].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 0) | (0x1 << 25),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 0) | (0x1 << 25));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_cmd[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 2) | (0x1 << 3) | (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 6) | (0x3 << 14) | (0x1 << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 6) | (0x0 << 14) | (0x0 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.pll3, (0x1 < 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dq[3], (0x1 << 3));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dq[3], (0x1 << 3));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].pll[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x3 << 18),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 0) | (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].pll[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].pll[11],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].pll[10],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PLL EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MID FINE_TUNE Init 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.pll4,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 18) | (0x1 << 21), (0x3 << 18) | (0x0 << 21));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].pll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 0), (0x3 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], (0x1 << 21));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[b].dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 1) | (0x1 << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].ca_dll[0], (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[1].phy.shu[0].ca_dll[0], (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x3 << 9) | (0xf << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 16) | (0xf << 20) | (0x1 << 30),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 4) | (0x3 << 9) | (0x8 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], (0x3f << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x7 << 12) | (0x1 << 20),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x4 << 12) | (0x1 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 6), (0x3 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[1].phy.shu[0].ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 6), (0x1 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffff << 6), 0x1 << 6);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.misc_shu_opt,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x3 << 2) | (0x1 << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 10) | (0x1 << 16) | (0x3 << 18),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x2 << 2) | (0x1 << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 10) | (0x1 << 16) | (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[1].phy.misc_shu_opt,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x3 << 2) | (0x1 << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 10) | (0x1 << 16) | (0x3 << 18),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x2 << 2) | (0x1 << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 10) | (0x1 << 16) | (0x2 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(9);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 2), (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 2), (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.pll2, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xFFFFFFFF, 0xF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ ddr_phy_reserved_rg_setting();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ ddr_phy_pll_setting(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.drsctrl, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Run time MRR CKE fix to 1 in tMRRI old mode</span><br><span style="color: hsl(120, 100%, 40%);">+ * to avoid no ACK from precharge all */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.ckectrl, (0x1 << 27));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.dramctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 15) | (0x1 << 17) | (0x1 << 23),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 15) | (0x1 << 17) | (0x1 << 23));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.spcmdctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[0].dq[9], (0x1 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[1].dq[9], (0x1 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0) | (0xf << 8) | (0xf << 16) | (0xf << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.stbcal1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x1 << 8) | (0x1 << 12),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x1 << 8) | (0x0 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 3) | (0xf << 8) | (0x1 << 21) | (0x1 << 31),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 3) | (0x6 << 8) | (0x1 << 21) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t i = 0; i < 4; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[i],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 0) | (0x1f << 5) | (0x1f << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (0x1f << 15) | (0x1f << 20) | (0x1f << 25),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xa << 0) | (0xa << 5) | (0xa << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+ | (0xa << 15) | (0xa << 20) | (0xa << 25));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shuctrl2,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0) | (0x1 << 12) | (0x1 << 14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 15) | (0xff << 16) | (0x1 << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xa << 0) | (0x1 << 12) | (0x1 << 14) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 15) | (0x1 << 16) | (0x0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dvfsdll, (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.ddrconf0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 12) | (0x1 << 15) | (0x1 << 20) | (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.stbcal2,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x1 << 28) | (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.stbcal2, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.stbcal2, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.clkar, (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[b].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 20), (0x1 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_cmd[10],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 20), (0x0 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cbt_mode(params) == CBT_BYTE_MODE1)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.misc_ctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0) | (0x1 << 9) | (0x7 << 18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 24) | (0x1 << 31),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0) | (0x1 << 9) | (0x1 << 18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 24) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_ctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b0_rxdvs[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 24), (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b1_rxdvs[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 24), (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_rxdvs0, (0x1 << 24), (0x0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.ca_cmd[7], (0x1 << 4)|(0x1 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.b[0].dq[7], (0x1 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].conf[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0) | (0x1 << 7) | (0xf << 12) | (0x1 << 24) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 29) | (0x3 << 30),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0) | (0x1 << 7) | (0x1 << 12) | (0x1 << 24) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 29) | (0x2 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].odtctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x7f << 16) | (0x1 << 30) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 31),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 16) | (0x1 << 30) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.refctrl0, (0xf << 24), (0x5 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].selph_ca1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].selph_ca2,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 0) | (0x0 << 4) | (0x0 << 8) | (0x7 << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].selph_ca3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].selph_ca4,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].selph_ca5, (0x7 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x5 << 0) | (0x5 << 4) | (0x5 << 8) | (0x5 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t i = 0; i < 2; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[i].selph_dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[i].selph_dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[i].selph_dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[i].selph_dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].rk[0].b[b].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 8) | (0x3f << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1a << 8) | (0x1a << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].rk[1].b[b].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 8) | (0x3f << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x14 << 8) | (0x14 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.b[b].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 14), (0x1 << 14));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.stbcal, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.srefctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 24) | (0x1 << 30), (0x8 << 24) | (0x0 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].ckectrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 24) | (0x3 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 24) | (0x3 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.rkcfg, (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cbt_mode(params) == CBT_BYTE_MODE1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].conf[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x1 << 28), (0x7 << 16) | (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.spcmdctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 26), (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shuctrl1, (0xff << 0), (0x40 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].conf[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x1 << 28), (0x7 << 16) | (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.spcmdctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 26), (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shuctrl1, (0xff << 0), (0x40 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shuctrl, (0x1 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.refctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 15) | (0x0 << 23));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dramctrl, (0x1 << 9));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.misctl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 19) | (0x1 << 24) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.perfctl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 4) | (0x1 << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 9) | (0x1 << 10) | (0x1 << 11) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 14) | (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.arbctl, (0xff << 0), (0x80 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.padctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dramc_pd_ctrl, (0x1 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.clkctrl, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.refctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 20) | (0xf << 24) | (0xf << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x4 << 20) | (0x4 << 24) | (0x6 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cbt_mode(params) == CBT_NORMAL_MODE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[0].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dramctrl, (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.zqcs, (0xff << 0), (0x56 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].conf[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1ff << 16), (0xff << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.refctrl0, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.srefctrl, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.mpc_option, (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dramc_pd_ctrl, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dramc_pd_ctrl, (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.eyescan,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.test2_1, (0xfffffff << 4), (0x10000 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.test2_2, (0xfffffff << 4), (0x400 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 7) | (0x7 << 8) | (0x1 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 7) | (0x4 << 8) | (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.rstmask, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.rstmask, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x8 << 0) | (0x6 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cbt_mode(params) == CBT_BYTE_MODE1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.perfctl0, (0x1 << 27));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.perfctl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.rstmask, (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.rkcfg, (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.eyescan, (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dramctrl, (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.perfctl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 18) | (0x1 << 19),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 18) | (0x1 << 19));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.rstmask, (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.rkcfg, (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.mpc_option, (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.eyescan, (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[0].wodt, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rankctl, (0xf << 20),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x4 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t r = 0; r < 2; r++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 0) | (0x2 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 0) | (0x7 << 4),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x2 << 0) | (0x2 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(5);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.stbcal1, (0xffff << 16), (0x3 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.stbcal1, (0xffff << 16), (0x1 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.stbcal,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 22) | (0x1 << 24) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 26) | (0x1 << 27),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x0 << 22) | (0x0 << 24) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 26) | (0x1 << 27));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.stbcal1, (0x1 << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].dqsg,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.misc_ctrl0, (0xf << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[0].stbcal, (0x1 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.stbcal, (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 14));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 14));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].stbcal, (0x7 << 4), (0x1 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].stbcal, (0x3 << 0), (0x2 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.rstmask,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 24) | (0x1 << 25) | (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.rkcfg, (0x7 << 4), (0x1 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(12);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cbt_mode(params) == CBT_BYTE_MODE1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 20) | (0xf << 24) | (0xf << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 20) | (0x3 << 24) | (0x5 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 24) | (0xf << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x4 << 24) | (0x6 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].wodt, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cbt_mode(params) == CBT_BYTE_MODE1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[0].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[0].fine_tune,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1a << 0) | (0x1a << 8) | (0x1a << 16) | (0x1a << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[0].selph_dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[0].selph_dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cbt_mode(params) == CBT_BYTE_MODE1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[1].fine_tune,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[1].selph_dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].rk[1].selph_dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 2) | (0xf << 8) | (0x1 << 14) | (0x3 << 24),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 2) | (0x5 << 8) | (0x0 << 14) | (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_cbt_mode(params) == CBT_BYTE_MODE1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 12) | (0x1 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.shu[0].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 12) | (0x1 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, (0x1f << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ update_initial_settings();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.test2_4, (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].conf[3], (0x1ff << 0), (0x5 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ delay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.refctrl0, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.dramctrl, (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.dummy_rd,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x1 << 11) | (0x1 << 13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 14) | (0x3 << 16) | (0x1 << 22),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x1 << 11) | (0x1 << 13) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 14) | (0x2 << 16) | (0x1 << 22));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.test2_4, (0x7 << 28), (0x4 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dramctrl, (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shuctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5)|(0x1 << 17), (0x0 << 5)|(0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[1].ao.shuctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5)|(0x1 << 17), (0x1 << 5)|(0x0 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[1].ao.shuctrl2, (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 clkDelay = params->clk_delay;</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 dqsDelay[CHANNEL_NUM] = {params->dqs_delay[CHANNEL_A],</span><br><span style="color: hsl(120, 100%, 40%);">+ params->dqs_delay[CHANNEL_B]};</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("%s param: clkdelay:0x%x,"</span><br><span style="color: hsl(120, 100%, 40%);">+ " dqsDelay[0]:0x%x, dqsDelay[1]:0x%x\n", __func__,</span><br><span style="color: hsl(120, 100%, 40%);">+ clkDelay, dqsDelay[0], dqsDelay[1]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_duty_calibration(CHANNEL_A, clkDelay, dqsDelay[CHANNEL_A]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_duty_calibration(CHANNEL_B, clkDelay, dqsDelay[CHANNEL_B]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_ac_timing_optimize(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[ACTiming Optimize] For MR8[5:2] = 4 sample only\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("16Gb per die (8Gb per channel)\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 16), (0x64 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, (0x1 << 2));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim[4],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3ff << 0), (0x77 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void ddr_update_ac_timing(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 temp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 24) | (0x7 << 16) | (0x1f << 8) | (0xf << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x6 << 24) | (0x2 << 16) | (0xc << 8) | (0x7 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 24) | (0xf << 16) | (0xf << 8) | (0x7 << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x10 << 24) | (0x8 << 16) | (0x5 << 8) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 24) | (0xf << 16) | (0x7 << 8) | (0x7 << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 24) | (0x7 << 16) | (0x2 << 8) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 16) | (0xff << 24) | (0xff << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x64 << 16) | (0x61 << 24) | (0x2c << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim[4],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 24) | (0xff << 16) | (0x3ff << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x22 << 24) | (0x65 << 16) | (0x77 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 24) | (0x1f << 8) | (0x1f << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xa << 24) | (0xc << 8) | (0xb << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 24) | (0x7 << 16) | (0xf << 8) | (0x1f << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x5 << 24) | (0x3 << 16) | (0x6 << 8) | (0x9 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 25) | (0x0 << 24) | (0x1 << 16) | (0x0 << 15)|</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x1 << 9) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 4) | (0x1 << 2) | (0x1 << 1) | (0x1 << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 25) | (0x0 << 24) | (0x1 << 16) | (0x0 << 15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 13) | (0x0 << 12) | (0x1 << 10) | (0x1 << 9) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 4) | (0x0 << 2) | (0x0 << 1) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.catraining1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 24) | (0xf << 20), (0xb << 24) | (0x0 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQSINCTL related */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0), (0x4 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0), (0x4 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].odtctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 4), (0x4 << 4));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DATLAT related, tREFBW */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].conf[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 0) | (0x1f << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 26) | (0x3ff << 16),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0) | (0xd << 8) | (0xd << 26) | (0x0 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].conf[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xff << 8), (0x64 << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].scintv,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 13) | (0x1f << 6), (0xf << 13) | (0xc << 6));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CKEPRD - CKE pulse width */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].ckectrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 20), (0x2 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CKELCKCNT: Valid clock requirement after CKE input low */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.ckectrl, (0x7 << 24), (0x0 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ininital setting values are the same,</span><br><span style="color: hsl(120, 100%, 40%);">+ * RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1</span><br><span style="color: hsl(120, 100%, 40%);">+ * XRTR2R setting will be updated in RxdqsGatingPostProcess */</span><br><span style="color: hsl(120, 100%, 40%);">+ temp = (read32(&ch[chn].ao.shu[0].rankctl) & 0x00f00000) >> 20;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0), (temp << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1ROOT = 0, u1TXRANKINCTL = 1, u1TXDLY = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 16) | (0xf << 12) | (0xf << 8),</span><br><span style="color: hsl(120, 100%, 40%);">+ (u1ROOT << 16) | (u1TXRANKINCTL << 12) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (u1TXDLY << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_init(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dram_t = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dram_cbt_mode, dram_cbt_mode_r0, dram_cbt_mode_r1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_setting(params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ddr_update_ac_timing();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.arbctl, (0x3 << 10), (dram_t << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_cbt_mode = get_cbt_mode(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_cbt_mode_r0 = dram_cbt_mode_r1 = dram_cbt_mode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.rstmask, (0x3 << 13), dram_cbt_mode);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.arbctl, (0x1 << 13),</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_cbt_mode_r0 | dram_cbt_mode_r1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>new file mode 100644</span><br><span>index 0000000..f08a659</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c</span><br><span>@@ -0,0 +1,2626 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_register.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_pi_api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/infracfg.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP 64</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMP_LP4X_TERM_VREF_SEL 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMP_DRVP_LP4X_UNTERM_VREF_SEL 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMP_DRVN_LP4X_UNTERM_VREF_SEL 0x16</span><br><span style="color: hsl(120, 100%, 40%);">+#define IMP_TRACK_LP4X_UNTERM_VREF_SEL 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DQ_DIV_SHIFT = 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ OEN_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_VREF_BEGIN = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_VREF_END = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_VREF_STEP = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_VREF_BEGIN = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_VREF_END = 18,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_VREF_STEP = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ FIRST_DQ_DELAY = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ FIRST_DQS_DELAY = -27,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_DQDLY_TAPS = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_RX_DQDLY_TAPS = 63,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_TX_DQDLY_TAPS = 200,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_TX_DQSDLY_TAPS = 63,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_RX_DQSDLY_TAPS = 26</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_WIN = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ STAGE_SETUP = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ STAGE_HOLD = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ STAGE_SETUP_RX_WIN = STAGE_SETUP | RX_WIN << 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ STAGE_HOLD_RX_WIN = STAGE_HOLD | RX_WIN << 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ STAGE_PRE_HOLD_RX_WIN,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_WIN_MOVE_DQ_ONLY,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_WIN_MOVE_DQ_DQM,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_DQ = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_DQM,</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_DQS,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQ,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQS,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQM</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dqs_perbit_dly {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 vref;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 last_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 last_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 best_first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 best_last_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 best_first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 best_last_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 best_dqdly;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 best_dqsdly;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct tx_dly_coarse_fine_tune {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 fine_tune;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 coarse_tune_large;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 coarse_tune_small;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 coarse_tune_large_oen;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 coarse_tune_small_oen;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct per_byte_dly {</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 max_center;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 min_center;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 final_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void auto_refresh_switch(u8 chn, u8 option)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (option == ENABLE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable autorefresh */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* disable autorefresh */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* because HW will actually disable autorefresh</span><br><span style="color: hsl(120, 100%, 40%);">+ * after refresh_queue empty, we need to wait quene empty */</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(((read32(&ch[chn].nao.misc_statusa) &</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STATUSA_REFRESH_QUEUE_CNT_MASK) >></span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT)*4);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rank_swap(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 multi_rank = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[RankSwap] (Multi %d), Rank %d\n", multi_rank, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.rkcfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ RKCFG_RKMODE_MASK | 1 << RKCFG_RKSWAP_SHIFT | RKCFG_TXRANK_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (multi_rank << RKCFG_RKMODE_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (rank << RKCFG_RKSWAP_SHIFT) | (rank << RKCFG_TXRANK_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TXRANK should be set before TXRANKFIX */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.rkcfg,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << RKCFG_TXRANKFIX_SHIFT, rank << RKCFG_TXRANKFIX_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void move_dramc_dq_common(uint32_t *reg_0p5t, uint32_t *reg_2t,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 shift, s8 shift_coarse_tune)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ s32 tmp_0p5t, tmp_2t;</span><br><span style="color: hsl(120, 100%, 40%);">+ s32 sum = (((read32(reg_2t) >> shift) & DQ_DIV_MASK) << DQ_DIV_SHIFT) +</span><br><span style="color: hsl(120, 100%, 40%);">+ ((read32(reg_0p5t) >> shift) & DQ_DIV_MASK) +</span><br><span style="color: hsl(120, 100%, 40%);">+ shift_coarse_tune;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sum < 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ sum = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_0p5t = sum & DQ_DIV_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_2t = sum >> DQ_DIV_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(reg_0p5t, DQ_DIV_MASK << shift, tmp_0p5t << shift);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(reg_2t, DQ_DIV_MASK << shift, tmp_2t << shift);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void move_dramc_tx_dqs(u8 chn, u8 byte_idx, s8 shift_coarse_tune)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_dq_common(&ch[chn].ao.shu[0].selph_dqs1,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.shu[0].selph_dqs0,</span><br><span style="color: hsl(120, 100%, 40%);">+ byte_idx * 4, shift_coarse_tune);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void move_dramc_tx_dqs_oen(u8 chn, u8 byte_idx,</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 shift_coarse_tune)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_dq_common(&ch[chn].ao.shu[0].selph_dqs1,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.shu[0].selph_dqs0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (byte_idx * 4) + OEN_SHIFT, shift_coarse_tune);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void move_dramc_tx_dq(u8 chn, u8 rank, u8 byte_idx, s8 shift_coarse_tune)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_dq_common(&ch[chn].ao.shu[0].rk[rank].selph_dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.shu[0].rk[rank].selph_dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ byte_idx * 4, shift_coarse_tune);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_dq_common(&ch[chn].ao.shu[0].rk[rank].selph_dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.shu[0].rk[rank].selph_dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ byte_idx * 4, shift_coarse_tune);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void move_dramc_tx_dq_oen(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 byte_idx, s8 shift_coarse_tune)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_dq_common(&ch[chn].ao.shu[0].rk[rank].selph_dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.shu[0].rk[rank].selph_dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (byte_idx * 4) + OEN_SHIFT, shift_coarse_tune);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_dq_common(&ch[chn].ao.shu[0].rk[rank].selph_dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.shu[0].rk[rank].selph_dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (byte_idx * 4) + OEN_SHIFT, shift_coarse_tune);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void write_leveling_move_dqs_instead_of_clk(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 byte_idx = 0; byte_idx < DQS_NUMBER; byte_idx++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_tx_dqs(chn, byte_idx, -1);</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_tx_dqs_oen(chn, byte_idx, -1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 i = RANK_0; i < RANK_MAX; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_tx_dq(chn, i, byte_idx, -1);</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_tx_dq_oen(chn, i, byte_idx, -1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rank = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4reg_024;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u4reg_024 = read32(&ch[chn].ao.ckectrl);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_FIXON, chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSMA_MASK, mr_idx << MRS_MRSMA_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSOP_MASK, value << MRS_MRSOP_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ while ((read32(&ch[chn].nao.spcmdresp) & 1) == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("wait MRW command fired\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.ckectrl, u4reg_024);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rank = (read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK) >></span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSRK_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("Write Rank%d MR%d =0x%x\n", rank, mr_idx, value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_mode_reg_write_by_rank(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mr_idx, u8 value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4RabnkBackup;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u4RabnkBackup = (read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK) >> 24;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write(chn, mr_idx, value);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSRK_MASK, u4RabnkBackup << MRS_MRSRK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_write_leveling(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ s32 wrlevel_dq_delay[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ s32 wrlevel_dqs_final_delay[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ s32 clock_delay_max = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("chn:%d, rank:%d params write level:0x%x, 0x%x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ chn, rank, params->wr_level[chn][rank][0],</span><br><span style="color: hsl(120, 100%, 40%);">+ params->wr_level[chn][rank][1]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ wrlevel_dqs_final_delay[0] = params->wr_level[chn][rank][0];</span><br><span style="color: hsl(120, 100%, 40%);">+ wrlevel_dqs_final_delay[1] = params->wr_level[chn][rank][1];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rank_swap(chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (rank == RANK_0)</span><br><span style="color: hsl(120, 100%, 40%);">+ write_leveling_move_dqs_instead_of_clk(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("No need to update CA/CS dly (CLK dly smaller than CA training)\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ clock_delay_max << SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("Final Clk output dly = %d\n", clock_delay_max);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("DQS%zd dly: %d\n", i, wrlevel_dqs_final_delay[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_PBYTE_B0_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ wrlevel_dqs_final_delay[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_PBYTE_B0_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_PBYTE_B1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ wrlevel_dqs_final_delay[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_PBYTE_B1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ wrlevel_dq_delay[i] = wrlevel_dqs_final_delay[i] + 0x10;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (wrlevel_dq_delay[i] >= 0x40) {</span><br><span style="color: hsl(120, 100%, 40%);">+ wrlevel_dq_delay[i] -= 0x40;</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_tx_dq(chn, rank, i, 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ move_dramc_tx_dq_oen(chn, rank, i, 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("chn:%d, rank:%d, dq_delay: 0x%x, 0x%x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ chn, rank, wrlevel_dq_delay[0], wrlevel_dq_delay[1]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQM_B0_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQ_B0_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (wrlevel_dq_delay[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQM_B0_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (wrlevel_dq_delay[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQ_B0_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQM_B1_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQ_B1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (wrlevel_dq_delay[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQM_B1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (wrlevel_dq_delay[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQ_B1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rank_swap(chn, RANK_0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void cmd_bus_training(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cbt_cs, i_mr12_value;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cbt_cs = params->cbt_cs[chn][rank];</span><br><span style="color: hsl(120, 100%, 40%);">+ i_mr12_value = params->cbt_mr12[chn][rank];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("start chn:%d, rank:%d, "</span><br><span style="color: hsl(120, 100%, 40%);">+ "cbt_cs:0x%x, mr12_value:0x%x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ chn, rank, cbt_cs, i_mr12_value);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* cbt_adjust_cs */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ cbt_cs << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* cbt_set_vref */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, rank, 12, i_mr12_value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_gating_mode(u8 chn, u8 mode)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 VrefSel = 0, BurstE2 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mode == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ VrefSel = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ BurstE2 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ VrefSel = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ BurstE2 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal1, (0x1 << 5), (BurstE2 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.stbcal, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[b].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 14), (VrefSel << 14));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void rx_dqs_isi_pulse_cg_en(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("CH %d RX DQS ISI pulse CG: enable\n", chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void rx_dqs_isi_pulse_cg_dis(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("CH %d RX DQS ISI pulse CG: disable\n", chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dram_phy_reset(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << MISC_CTRL1_R_DMPHYRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (1 << 4) | (1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (1 << 4) | (1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (1 << 4) | (1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dq[9],</span><br><span style="color: hsl(120, 100%, 40%);">+ (1 << 4) | (1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.misc_ctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << MISC_CTRL1_R_DMPHYRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.ddrconf0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << DDRCONF0_RDATRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 *pass_begin,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *pass_count, u8 *dly_fine_xt, u32 *coarse_tune, u8 *dqs_high)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pass_byte_count = 0, current_pass = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 debug_cnt_perbyte;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pass_count_1[DQS_NUMBER], min_coarse_tune2t_1[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune0p5t_1[DQS_NUMBER], min_fine_tune_1[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_start = 18;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_end = coarse_start + 24;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pass_byte_count & (1 << dqs))</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs_result_r = (u8) ((result_r >> (8 * dqs)) & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs_result_f = (u8) ((result_f >> (8 * dqs)) & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ debug_cnt_perbyte = (u16) debug_cnt[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current_pass = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((dqs_result_r == 0) && (dqs_result_f == 0) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (debug_cnt_perbyte == GATING_GOLDEND_DQSCNT))</span><br><span style="color: hsl(120, 100%, 40%);">+ current_pass = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (current_pass) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pass_begin[dqs] == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_begin[dqs] = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_count_1[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune2t_1[dqs] = dly_coarse_large;</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune0p5t_1[dqs] = dly_coarse_0p5t;</span><br><span style="color: hsl(120, 100%, 40%);">+ min_fine_tune_1[dqs] = *dly_fine_xt;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[Byte %d]First pass (%d, %d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, dly_coarse_large,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t, *dly_fine_xt);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pass_begin[dqs] == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_count_1[dqs]++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((pass_begin[dqs] == 1) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (pass_count_1[dqs] * DQS_GW_FINE_STEP > 32))</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((pass_count_1[0] * DQS_GW_FINE_STEP > 32) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (pass_count_1[1] * DQS_GW_FINE_STEP > 32)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("All bytes gating window > 1 "</span><br><span style="color: hsl(120, 100%, 40%);">+ "coarse_tune, Early break\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ *dly_fine_xt = 32;</span><br><span style="color: hsl(120, 100%, 40%);">+ *coarse_tune = coarse_end;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void find_dly_tune(u8 chn, u8 dly_coarse_large, u8 dly_coarse_0p5t,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_fine_xt, u8 *dqs_cnt1, u8 *dqs_cnt2, u8 *dqs_high,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *dly_coarse_large_cnt, u8 *dly_coarse_0p5t_cnt,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *dly_fine_tune_cnt, u8 *dqs_transition)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqs == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_cnt1[0] =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].phy_nao.misc_phy_stben_b0)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> 16) & 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_cnt2[0] =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].phy_nao.misc_phy_stben_b0)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> 17) & 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_cnt1[1] =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].phy_nao.misc_phy_stben_b1)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> 16) & 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_cnt2[1] =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].phy_nao.misc_phy_stben_b1)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> 17) & 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((dqs_cnt1[dqs] == 1) && (dqs_cnt2[dqs] == 1))</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[dqs]++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqs_high[dqs] * DQS_GW_FINE_STEP <= 16)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((dqs_cnt1[dqs] == 1) && (dqs_cnt2[dqs] == 1)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large_cnt[dqs] = dly_coarse_large;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_cnt[dqs] = dly_coarse_0p5t;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_tune_cnt[dqs] = dly_fine_xt;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_transition[dqs] = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (((dqs_cnt1[dqs] == 1) && (dqs_cnt2[dqs] == 0)) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ ((dqs_cnt1[dqs] == 0) && (dqs_cnt2[dqs] == 1))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqs_transition[dqs] == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[Byte %d] cnt1/cnt2 falling Transition"</span><br><span style="color: hsl(120, 100%, 40%);">+ " (%d, %d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, dly_coarse_large_cnt[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_cnt[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_tune_cnt[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_transition[dqs]++;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if ((dqs_cnt1[dqs] == 0) && (dqs_cnt2[dqs] == 0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[Byte %d] cnt1/cnt2 Transition tap number (%d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, dqs_transition[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pass_begin[DQS_NUMBER], pass_count[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 min_coarse_tune2t[DQS_NUMBER], min_coarse_tune0p5t[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ min_fine_tune[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 best_fine_tune[DQS_NUMBER], best_coarse_tune0p5t[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 best_fine_tune_p1[DQS_NUMBER], best_coarse_tune0p5t_p1[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 best_coarse_large_rodt[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 best_coarse_large_rodt_p1[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt_p1[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_start = 8, coarse_end = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 debug_cnt[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs_cnt1[DQS_NUMBER], dqs_cnt2[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[DQS_NUMBER], dqs_transition[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_coarse_large_cnt[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_cnt[DQS_NUMBER],</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_tune_cnt[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mr1_value[FSP_MAX] = { 0x56, 0x56 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *u4RegBackup[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.stbcal,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.stbcal1,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.ddrconf0,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.spcmd,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.refctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].phy.b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].phy.b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_restore_multi_reg(SAVE_VALUE,</span><br><span style="color: hsl(120, 100%, 40%);">+ u4RegBackup, ARRAY_SIZE(u4RegBackup));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rx_dqs_isi_pulse_cg_dis(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value[1] | 0x80);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_PBREFEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_hw_gating_onoff(chn, GATING_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBENCMPEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBCNT_LATCH_EN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_DM4TO1MODE_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.misc_ctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ rank << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_init(chn, rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEFAULT_TEST2_1_CAL, 0xaa000000 | GATING_PATTERN_NUM,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_AUDIO_PATTERN, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_begin[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_count[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_cnt1[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_cnt2[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_high[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_transition[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large_cnt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_cnt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_tune_cnt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("[Gating]\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_start = 18;</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_end = coarse_start + 24;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end;</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune += DQS_GW_COARSE_STEP) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_large_rodt = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_0p5t_rodt = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_large_rodt_p1 = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_0p5t_rodt_p1 = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_large_p1 =</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune + DQS_GW_FREQ_DIV) / RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dly_coarse_0p5t_p1 =</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune + DQS_GW_FREQ_DIV) % RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (value >= 11) {</span><br><span style="color: hsl(120, 100%, 40%);">+ value -= 11;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large_rodt = value >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_rodt =</span><br><span style="color: hsl(120, 100%, 40%);">+ value - (dly_coarse_large_rodt << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large_rodt_p1 = value >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_0p5t_rodt_p1 =</span><br><span style="color: hsl(120, 100%, 40%);">+ value - (dly_coarse_large_rodt_p1 << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) dly_coarse_large <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) dly_coarse_large <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) dly_coarse_0p5t <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) dly_coarse_0p5t <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_rodt <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_rodt <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_rodt_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_large_rodt_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_rodt <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_rodt <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_rodt_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (dly_coarse_0p5t_rodt_p1 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 dly_fine_xt = DQS_GW_FINE_START;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt < DQS_GW_FINE_END;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt += DQS_GW_FINE_STEP) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_gating_mode(chn, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt | (dly_fine_xt << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << SPCMD_DQSGCNTRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << SPCMD_DQSGCNTRST_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_run(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_READ_CHECK, TEST_AUDIO_PATTERN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 result_r =</span><br><span style="color: hsl(120, 100%, 40%);">+ read32(&ch[chn].phy.misc_stberr_rk0_r)</span><br><span style="color: hsl(120, 100%, 40%);">+ & MISC_STBERR_RK_R_STBERR_RK_R_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 result_f =</span><br><span style="color: hsl(120, 100%, 40%);">+ read32(&ch[chn].phy.misc_stberr_rk0_f)</span><br><span style="color: hsl(120, 100%, 40%);">+ & MISC_STBERR_RK_F_STBERR_RK_F_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ debug_cnt[0] &= 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_gating_mode(chn, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_run(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_READ_CHECK, TEST_AUDIO_PATTERN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ find_dly_tune(chn, dly_coarse_large, dly_coarse_0p5t,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt, &dqs_cnt1[0], &dqs_cnt2[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ &dqs_high[0], &dly_coarse_large_cnt[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ &dly_coarse_0p5t_cnt[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ &dly_fine_tune_cnt[0], &dqs_transition[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("%d %d %d |",</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large, dly_coarse_0p5t,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_fine_xt);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("%X ", debug_cnt[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show(" |");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("(%X %X)",</span><br><span style="color: hsl(120, 100%, 40%);">+ (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff,</span><br><span style="color: hsl(120, 100%, 40%);">+ (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show(" |");</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("(%d %d)",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs_cnt1[dqs], dqs_cnt2[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ find_gating_window(result_r, result_f, &debug_cnt[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_coarse_large, dly_coarse_0p5t,</span><br><span style="color: hsl(120, 100%, 40%);">+ &pass_begin[0], &pass_count[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ &dly_fine_xt, &coarse_tune, &dqs_high[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_end(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pass_count[dqs] = dqs_transition[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ min_fine_tune[dqs] = dly_fine_tune_cnt[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 tmp_offset = pass_count[dqs] * DQS_GW_FINE_STEP / 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 tmp_value = min_fine_tune[dqs] + tmp_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_fine_tune[dqs] = tmp_value % RX_DLY_DQSIENSTB_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_fine_tune_p1[dqs] = best_fine_tune[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_offset = tmp_value / RX_DLY_DQSIENSTB_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value = min_coarse_tune0p5t[dqs] + tmp_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t[dqs] = tmp_value % RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_offset = tmp_value / RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ min_coarse_tune2t[dqs] + tmp_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value = best_coarse_tune0p5t[dqs] + DQS_GW_FREQ_DIV;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t_p1[dqs] = tmp_value % RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_offset = tmp_value / RX_DQS_CTL_LOOP;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[dqs] + tmp_offset;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("\nbest DQS%d dly(2T, 0.5T, fine tune)"</span><br><span style="color: hsl(120, 100%, 40%);">+ " = (%d, %d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, best_coarse_tune2t[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t[dqs], best_fine_tune[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("\nbest DQS%d best coarse dly"</span><br><span style="color: hsl(120, 100%, 40%);">+ "(2T, 0.5T, fine tune) = (%d, %d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs, best_coarse_tune2t_p1[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t_p1[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_fine_tune[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_restore_multi_reg(RESTORE_VALUE,</span><br><span style="color: hsl(120, 100%, 40%);">+ u4RegBackup, ARRAY_SIZE(u4RegBackup));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value[1] & 0x7f);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rx_dqs_isi_pulse_cg_en(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune2t[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune2t[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune2t_p1[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune2t_p1[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune0p5t[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune0p5t[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune0p5t_p1[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_tune0p5t_p1[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 tmp_value = (best_coarse_tune2t[dqs] << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+ + best_coarse_tune0p5t[dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tmp_value >= 11) {</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value -= 11;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt[dqs] = tmp_value >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt[dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value - (best_coarse_large_rodt[dqs] << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value = (best_coarse_tune2t_p1[dqs] << 3) +</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune0p5t_p1[dqs] - 11;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt_p1[dqs] = tmp_value >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt_p1[dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_value - (best_coarse_large_rodt_p1[dqs] << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("\nbest RODT dly(2T, 0.5T) = (%d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt[dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt[dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt[dqs] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_large_rodt_p1[dqs] = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_0p5t_rodt_p1[dqs] = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg</span><br><span style="color: hsl(120, 100%, 40%);">+ ("[RxdqsGatingCal] Error: best_coarse_tune2t[%d]"</span><br><span style="color: hsl(120, 100%, 40%);">+ " is already 0. RODT cannot be -1 coarse tune\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_large_rodt[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_large_rodt[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_large_rodt_p1[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_large_rodt_p1[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_0p5t_rodt[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_0p5t_rodt[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_0p5t_rodt_p1[0] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u32) best_coarse_0p5t_rodt_p1[1] <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].dqsien,</span><br><span style="color: hsl(120, 100%, 40%);">+ best_fine_tune[0] | (best_fine_tune[1] << 8));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[dramc_rx_dqs_gating_cal] Done\n\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_dqs_gating_post_process(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dqs, rank_rx_dvs, dbi_r_on = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rank, rank_max, rank_cur = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 change_dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 read_dqsinctl, read_rodt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 rankinctl_root, xrtr2r, reg_tx_dly_dqsgated_min = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 txdly_cal_min = 0xff, txdly_cal_max = 0, tx_dly_dqs_gated = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 best_coarse_tune2t[RANK_MAX][DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 best_coarse_tune2t_p1[RANK_MAX][DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg_tx_dly_dqsgated_min = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ rank_rx_dvs = reg_tx_dly_dqsgated_min - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_R_DMRANKRXDVS_B0_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ rank_rx_dvs << SHU1_B0_DQ7_R_DMRANKRXDVS_B0_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_R_DMRANKRXDVS_B1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ rank_rx_dvs << SHU1_B1_DQ7_R_DMRANKRXDVS_B1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (((read32(&ch[chn].ao.rstmask)>></span><br><span style="color: hsl(120, 100%, 40%);">+ RSTMASK_RSV_DRAM_SUPPORT_RANK_NUM_SHIFT) & 1) == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ rank_max = RANK_MAX;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ rank_max = RANK_1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < rank_max; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[rank][dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0) >></span><br><span style="color: hsl(120, 100%, 40%);">+ (dqs * 8)) &</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[rank][dqs] =</span><br><span style="color: hsl(120, 100%, 40%);">+ ((read32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0)</span><br><span style="color: hsl(120, 100%, 40%);">+ >> (dqs * 8)) &</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_MASK) >></span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("\nrank%d best DQS%d dly(2T, (P1)2T) = (%d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ (u32) rank, (u32) dqs,</span><br><span style="color: hsl(120, 100%, 40%);">+ (u32) best_coarse_tune2t[rank][dqs],</span><br><span style="color: hsl(120, 100%, 40%);">+ (u32) best_coarse_tune2t_p1[rank][dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tx_dly_dqs_gated = best_coarse_tune2t[rank][dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tx_dly_dqs_gated < txdly_cal_min)</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_min = tx_dly_dqs_gated;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tx_dly_dqs_gated = best_coarse_tune2t_p1[rank][dqs];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tx_dly_dqs_gated > txdly_cal_max)</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_max = tx_dly_dqs_gated;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ change_dqsinctl = reg_tx_dly_dqsgated_min - txdly_cal_min;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg</span><br><span style="color: hsl(120, 100%, 40%);">+ ("ChangeDQSINCTL %d, tx_dly_dqsgated_min %d, txdly_cal_min %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ change_dqsinctl, reg_tx_dly_dqsgated_min, txdly_cal_min);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (change_dqsinctl != 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_min += change_dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_max += change_dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < rank_max; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("Rank: %d\n", rank);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[rank][dqs] += change_dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[rank][dqs] += change_dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("best DQS%d dly(2T) = (%d)\n", dqs,</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t[rank][dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dqs = 0; dqs < DQS_NUMBER; dqs++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("best DQS%d P1 dly(2T) = (%d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ dqs,</span><br><span style="color: hsl(120, 100%, 40%);">+ best_coarse_tune2t_p1[rank][dqs]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < rank_max; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (best_coarse_tune2t[rank][0] << 0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (best_coarse_tune2t[rank][1] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (best_coarse_tune2t_p1[rank][0] << 4) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (best_coarse_tune2t_p1[rank][1] << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl = read32(&ch[chn].ao.shu[0].rk[rank_cur].dqsctl) &</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_DQSCTL_DQSINCTL_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl -= change_dqsinctl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dbi_r_on) {</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl++;</span><br><span style="color: hsl(120, 100%, 40%);">+ read_rodt =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].ao.shu[0].odtctrl) &</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_ODTCTRL_RODT_MASK) >> SHU_ODTCTRL_RODT_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].odtctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_ODTCTRL_RODT_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (read_rodt + 1) << SHU_ODTCTRL_RODT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (read_dqsinctl >= 3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ rankinctl_root = read_dqsinctl - 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ rankinctl_root = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("DQSINCTL < 3, Risk for supporting 1066/RL8\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_DQSCTL_DQSINCTL_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_DQSCTL_DQSINCTL_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_PHY_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl << SHU_RANKCTL_RANKINCTL_PHY_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ rankinctl_root << SHU_RANKCTL_RANKINCTL_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_ROOT1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ rankinctl_root << SHU_RANKCTL_RANKINCTL_ROOT1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ xrtr2r = 8 + txdly_cal_max + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (xrtr2r > 12) {</span><br><span style="color: hsl(120, 100%, 40%);">+ xrtr2r = 12;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("XRTR2R > 12, Max value is 12\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_ACTIM_XRT_XRTR2R_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ xrtr2r << SHU_ACTIM_XRT_XRTR2R_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ txdly_cal_min, txdly_cal_max, change_dqsinctl);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("DQSINCTL=%d, RANKINCTL=%d, XRTR2R=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ read_dqsinctl, rankinctl_root, xrtr2r);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rd_dqc_init(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *lpddr_phy_mapping;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 temp_value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mr15_golden_value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mr20_golden_value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 LPDDR4_PHY_Mapping_POP[CHANNEL_NUM][16] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CHA */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, 0, 2, 4, 3, 7, 5, 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ 9, 8, 12, 11, 10, 15, 13, 14</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CHB */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, 1, 5, 6, 3, 7, 4, 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ 9, 8, 12, 15, 11, 14, 13, 10</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << SHU1_B1_DQ7_R_DMDQMDBI_SHU_B1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if(rank == RANK_0)</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSRK_MASK, 0 << MRS_MRSRK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSRK_MASK, 1 << MRS_MRSRK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.mpc_option,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << MPC_OPTION_MPCRKEN_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ lpddr_phy_mapping = (u8 *)LPDDR4_PHY_Mapping_POP[chn];</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 16; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ temp_value |= ((0x5555 >> i) & 0x1) << lpddr_phy_mapping[i];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mr15_golden_value = (u8) temp_value & 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+ mr20_golden_value = (u8) (temp_value >> 8) & 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mr_golden,</span><br><span style="color: hsl(120, 100%, 40%);">+ MR_GOLDEN_MR15_GOLDEN_MASK | MR_GOLDEN_MR20_GOLDEN_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ mr15_golden_value << 8 | mr20_golden_value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 dramc_rd_dqc_run(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 timeout_cnt = 100;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 response;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 result;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ response =</span><br><span style="color: hsl(120, 100%, 40%);">+ read32(&ch[chn].nao.spcmdresp)</span><br><span style="color: hsl(120, 100%, 40%);">+ & (0x1 << SPCMDRESP_RDDQC_RESPONSE_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ timeout_cnt--;</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while ((response == 0) && (timeout_cnt > 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (timeout_cnt == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[RxWinRDDQC] Resp fail (time out)\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ result = read32(&ch[chn].nao.rdqc_cmp);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return result;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rd_dqc_end(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, 0 << MRS_MRSRK_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_vref_enable(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[0].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.b[1].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_set_rx_vref(u8 chn, u8 value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ value << SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ value << SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_set_tx_vref(u8 chn, u8 rank, u16 value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_mode_reg_write_by_rank(chn, rank, 14, value | 0 << 6);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_rx_dly_factor(u8 chn, u8 rank, u8 type, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 value;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 mask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (type) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case RX_DQ:</span><br><span style="color: hsl(120, 100%, 40%);">+ value = (val << 24 | val << 16 | val << 8 | val);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 2; i < 6; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[i],</span><br><span style="color: hsl(120, 100%, 40%);">+ value);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[i],</span><br><span style="color: hsl(120, 100%, 40%);">+ value);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ case RX_DQM:</span><br><span style="color: hsl(120, 100%, 40%);">+ value = (val << 8 | val);</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = SHU1_B0_DQ6_RK_RX_ARDQM0_F_DLY_B0_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ6_RK_RX_ARDQM0_R_DLY_B0_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ mask, value);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ mask, value);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ case RX_DQS:</span><br><span style="color: hsl(120, 100%, 40%);">+ value = (val << 24 | val << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = SHU1_B0_DQ6_RK_RX_ARDQS0_F_DLY_B0_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ6_RK_RX_ARDQS0_R_DLY_B0_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ mask, value);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ mask, value);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_transfer_dly_tune(u8 chn, u32 dly,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct tx_dly_coarse_fine_tune *dly_tune)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 tmp_val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune->fine_tune = dly & (TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_val = (dly / TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP) << 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune->coarse_tune_small = tmp_val - ((tmp_val >> 3) << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune->coarse_tune_large = tmp_val >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_val -= 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune->coarse_tune_small_oen = tmp_val - ((tmp_val >> 3) << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune->coarse_tune_large_oen = tmp_val >> 3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_tx_dly_factor(u32 chn, u8 rank, u8 type, u32 curr_val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct tx_dly_coarse_fine_tune dly_tune = { };</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_tune_large = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_tune_large_oen = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_tune_small = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_tune_small_oen = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_transfer_dly_tune(chn, curr_val, &dly_tune);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 4; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_large += dly_tune.coarse_tune_large << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_large_oen +=</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.coarse_tune_large_oen << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_small += dly_tune.coarse_tune_small << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_small_oen +=</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.coarse_tune_small_oen << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (type == TX_DQM)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("%3d |%d %d %2d | [0]", curr_val,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.coarse_tune_large,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.coarse_tune_small, dly_tune.fine_tune);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (type) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case TX_DQM:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* large coarse_tune setting */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_large_oen << 16) | coarse_tune_large);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_small_oen << 16) | coarse_tune_small);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_large_oen << 16) | coarse_tune_large);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_small_oen << 16) | coarse_tune_small);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* fine_tune delay setting */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQ_B0_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.fine_tune << 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQ_B1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.fine_tune << 8);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQM_B0_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.fine_tune << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQM_B1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.fine_tune << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ case TX_DQ:</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_large_oen << 16) | coarse_tune_large);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_small_oen << 16) | coarse_tune_small);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQ_B0_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.fine_tune << 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQ_B1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ dly_tune.fine_tune << 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_dly_factor(u8 chn, u8 rank, u8 type, u32 dly)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (type) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case TX_WIN_MOVE_DQ_ONLY:</span><br><span style="color: hsl(120, 100%, 40%);">+ set_tx_dly_factor(chn, rank, TX_DQ, dly);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ case TX_WIN_MOVE_DQ_DQM:</span><br><span style="color: hsl(120, 100%, 40%);">+ set_tx_dly_factor(chn, rank, TX_DQM, dly);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("%s Invalid type\n", __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_engine2_setpat(u8 chn, u8 testaudpat,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 log2loopcount, u8 Use_Len1_Flag)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (testaudpat == TEST_XTALK_PATTERN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (Use_Len1_Flag != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_3_TESTAUDPAT_SHIFT | TEST2_3_TESTCNT_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ log2loopcount << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TESTXTALKPAT_SHIFT |</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TESTAUDMODE_SHIFT |</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TESTAUDBITINV_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TESTXTALKPAT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 << TEST2_4_TESTSSOPAT_SHIFT |</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (testaudpat == TEST_AUDIO_PATTERN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINIT_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINC_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTXTALKPAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDMODE_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << TEST2_4_TESTAUDBITINV_SHIFT),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x11 << 8) | (0xd << 0) | (0x1 << 14));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_3_TESTAUDPAT_SHIFT | TEST2_3_TESTCNT_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_3_TESTAUDPAT_SHIFT | log2loopcount << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.test2_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_3_TESTAUDPAT_SHIFT | TEST2_3_TESTCNT_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ log2loopcount << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.test2_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << TEST2_4_TESTXTALKPAT_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 dram_k_perbit(u8 chn, u8 engine_type)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 err_value = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (engine_type) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_setpat(chn, TEST_AUDIO_PATTERN, 0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ err_value = dramc_engine2_run(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_WRITE_READ_CHECK, TEST_AUDIO_PATTERN);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_setpat(chn, TEST_XTALK_PATTERN, 0, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ err_value |= dramc_engine2_run(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_WRITE_READ_CHECK, TEST_XTALK_PATTERN);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else</span><br><span style="color: hsl(120, 100%, 40%);">+ err_value = dramc_rd_dqc_run(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ return err_value;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_check_dq_win(struct dqs_perbit_dly *p,</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 dly_step, s16 last_step, u32 fail_bit)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 dqdly_pass_win, best_pass_win;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (fail_bit == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (p->first_dqdly_pass == -1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* first DQ pass delay tap */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->first_dqdly_pass = dly_step;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((p->last_dqdly_pass == -2) && (dly_step == last_step)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* pass to the last tap */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqdly_pass = dly_step;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdly_pass_win =</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqdly_pass - p->first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_pass_win =</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_last_dqdly_pass</span><br><span style="color: hsl(120, 100%, 40%);">+ - p->best_first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqdly_pass_win > best_pass_win) {</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_last_dqdly_pass = p->last_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_first_dqdly_pass = p->first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* clear to find the next pass range if it has */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->first_dqdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((p->first_dqdly_pass != -1)</span><br><span style="color: hsl(120, 100%, 40%);">+ && (p->last_dqdly_pass == -2)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqdly_pass = dly_step - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdly_pass_win =</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqdly_pass - p->first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_pass_win =</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_last_dqdly_pass</span><br><span style="color: hsl(120, 100%, 40%);">+ - p->best_first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqdly_pass_win > best_pass_win) {</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_last_dqdly_pass = p->last_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_first_dqdly_pass = p->first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* clear to find the next pass range if it has */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->first_dqdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int dramk_calcu_best_vref(u8 cal_type,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dqs_perbit_dly vref_dly[], struct dqs_perbit_dly delay[],</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 min_win_size, u32 max_win_sum)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 bit;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 win_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 win_size_sum = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ static u32 min_win_size_vref;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cal_type == (RX_WIN | (1 << 1))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (bit = 0; bit < DQ_DATA_WIDTH; bit++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ win_size_sum +=</span><br><span style="color: hsl(120, 100%, 40%);">+ (delay[bit].best_last_dqdly_pass -</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_first_dqdly_pass + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ win_size_sum +=</span><br><span style="color: hsl(120, 100%, 40%);">+ (delay[bit].best_last_dqsdly_pass -</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_first_dqsdly_pass + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (win_size_sum > max_win_sum) {</span><br><span style="color: hsl(120, 100%, 40%);">+ max_win_sum = win_size_sum;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (bit = 0; bit < DQ_DATA_WIDTH; bit++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].vref = delay[bit].vref;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_dqdly =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_dqdly;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_first_dqdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_last_dqdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_last_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_first_dqsdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_last_dqsdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_last_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (win_size_sum < (max_win_sum * 95 / 100))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (cal_type == TX_DQ_DQS_MOVE_DQ_ONLY) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (bit = 0; bit < DQ_DATA_WIDTH; bit++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ win_size =</span><br><span style="color: hsl(120, 100%, 40%);">+ (delay[bit].best_last_dqdly_pass -</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_first_dqdly_pass + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (win_size < min_win_size)</span><br><span style="color: hsl(120, 100%, 40%);">+ min_win_size = win_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ win_size_sum += win_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((win_size_sum > max_win_sum)</span><br><span style="color: hsl(120, 100%, 40%);">+ && (min_win_size >= min_win_size_vref)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ max_win_sum = win_size_sum;</span><br><span style="color: hsl(120, 100%, 40%);">+ min_win_size_vref = min_win_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (bit = 0; bit < DQ_DATA_WIDTH; bit++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].vref = delay[bit].vref;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_dqdly =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_dqdly;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_first_dqdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_last_dqdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_last_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (bit = 0; bit < DQ_DATA_WIDTH; bit++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].vref = delay[bit].vref;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_dqdly = delay[bit].best_dqdly;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_first_dqdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_last_dqdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_last_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_first_dqsdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dly[bit].best_last_dqsdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ delay[bit].best_last_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 dramc_calcu_best_dly(u8 bit,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dqs_perbit_dly *p, u32 *p_max_byte)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 fail = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 hold, setup;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hold = p->best_last_dqsdly_pass - p->best_first_dqsdly_pass + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ setup = p->best_last_dqdly_pass - p->best_first_dqdly_pass + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hold > setup) {</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_dqdly = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_dqsdly = (setup != 0) ? (hold - setup) / 2 :</span><br><span style="color: hsl(120, 100%, 40%);">+ (hold - setup) / 2 + p->best_first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (p->best_dqsdly > *p_max_byte)</span><br><span style="color: hsl(120, 100%, 40%);">+ *p_max_byte = p->best_dqsdly;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (hold < setup) {</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_dqsdly = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_dqdly = (hold != 0) ? (setup - hold) / 2 :</span><br><span style="color: hsl(120, 100%, 40%);">+ (setup - hold) / 2 + p->best_first_dqdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ } else { /* hold time == setup time */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_dqsdly = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_dqdly = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hold == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("ERROR, error bit %d, "</span><br><span style="color: hsl(120, 100%, 40%);">+ "setup_time = hold_time = 0\n", bit);</span><br><span style="color: hsl(120, 100%, 40%);">+ fail = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ bit, setup, hold, setup + hold,</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_dqdly, p->best_dqsdly);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return fail;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_calcu_tx_perbyte_dly(u8 bit,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dqs_perbit_dly *p, struct per_byte_dly *byte_delay_prop)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 win_center;</span><br><span style="color: hsl(120, 100%, 40%);">+ win_center = (p->best_first_dqdly_pass + p->best_last_dqdly_pass) >> 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (win_center < byte_delay_prop->min_center)</span><br><span style="color: hsl(120, 100%, 40%);">+ byte_delay_prop->min_center = win_center;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (win_center > byte_delay_prop->max_center)</span><br><span style="color: hsl(120, 100%, 40%);">+ byte_delay_prop->max_center = win_center;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_tx_best_dly_factor(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct per_byte_dly *tx_perbyte_dly,</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 dq_precal_result[])</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i, rank_idx;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_tune_large = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_tune_large_oen = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_tune_small = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 coarse_tune_small_oen = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 dq_oen[DQS_NUMBER] = { }, dqm_oen[DQS_NUMBER] = { };</span><br><span style="color: hsl(120, 100%, 40%);">+ struct tx_dly_coarse_fine_tune perbyte_dqdly_tune[DQS_NUMBER] = { };</span><br><span style="color: hsl(120, 100%, 40%);">+ struct tx_dly_coarse_fine_tune perbyte_dqmdly_tune[DQS_NUMBER] = { };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_transfer_dly_tune(chn, tx_perbyte_dly[i].final_dly,</span><br><span style="color: hsl(120, 100%, 40%);">+ &perbyte_dqdly_tune[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_transfer_dly_tune(chn, dq_precal_result[i],</span><br><span style="color: hsl(120, 100%, 40%);">+ &perbyte_dqmdly_tune[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_large +=</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqdly_tune[i].coarse_tune_large << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_large_oen +=</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqdly_tune[i].coarse_tune_large_oen << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_small +=</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqdly_tune[i].coarse_tune_small << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_small_oen +=</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqdly_tune[i].coarse_tune_small_oen << (i * 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ dq_oen[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ (perbyte_dqdly_tune[i].coarse_tune_large_oen << 3) +</span><br><span style="color: hsl(120, 100%, 40%);">+ (perbyte_dqdly_tune[i].coarse_tune_small_oen << 5) +</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqdly_tune[i].fine_tune;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqm_oen[i] =</span><br><span style="color: hsl(120, 100%, 40%);">+ (perbyte_dqmdly_tune[i].coarse_tune_large_oen << 3) +</span><br><span style="color: hsl(120, 100%, 40%);">+ (perbyte_dqmdly_tune[i].coarse_tune_small_oen << 5) +</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqmdly_tune[i].fine_tune;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank_idx = rank; rank_idx < RANK_MAX; rank_idx++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank_idx].selph_dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_large_oen << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_large);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank_idx].selph_dq[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_small_oen << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_small);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank_idx].selph_dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_large_oen << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_large);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].rk[rank_idx].selph_dq[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (coarse_tune_small_oen << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ coarse_tune_small);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank_idx = rank; rank_idx < RANK_MAX; rank_idx++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank_idx].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQ_B0_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQM_B0_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqdly_tune[0].fine_tune <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQ_B0_SHIFT |</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqmdly_tune[0].fine_tune <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQM_B0_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank_idx].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQ_B1_MASK |</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQM_B1_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqdly_tune[1].fine_tune <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQ_B1_SHIFT |</span><br><span style="color: hsl(120, 100%, 40%);">+ perbyte_dqmdly_tune[1].fine_tune <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQM_B1_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_rx_best_dly_factor(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dqs_perbit_dly *dqdqs_perbit_dly,</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *max_dqsdly_byte, u32 *ave_dqm_dly)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 i, value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 index, byte;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ value = (max_dqsdly_byte[i] << 24) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (max_dqsdly_byte[i] << 16) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (ave_dqm_dly[i] << 8) | (ave_dqm_dly[i] << 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Delay dqs/dqm */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[6], value);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQ_DATA_WIDTH; i += 2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = i / DQS_BIT_NUMBER;</span><br><span style="color: hsl(120, 100%, 40%);">+ index = 2 + ((i % 8) * 2) / 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ value =</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i + 1].best_dqdly << 24 |</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i + 1].best_dqdly << 16 |</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].best_dqdly << 8 |</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].best_dqdly;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[index],</span><br><span style="color: hsl(120, 100%, 40%);">+ value);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_get_vref_range(u8 cal_type, u8 enable,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *begin, u8 *end, u8 *step)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (enable) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cal_type == RX_WIN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ *begin = RX_VREF_BEGIN;</span><br><span style="color: hsl(120, 100%, 40%);">+ *end = RX_VREF_END;</span><br><span style="color: hsl(120, 100%, 40%);">+ *step = RX_VREF_STEP;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (cal_type == TX_WIN_MOVE_DQ_ONLY) {</span><br><span style="color: hsl(120, 100%, 40%);">+ *begin = TX_VREF_BEGIN;</span><br><span style="color: hsl(120, 100%, 40%);">+ *end = TX_VREF_END;</span><br><span style="color: hsl(120, 100%, 40%);">+ *step = TX_VREF_STEP;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ *begin = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ *end = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ *step = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 dramc_get_smallest_dqs_dly(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dq_coarse_dly = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 dq_fine_dly = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tmp_dly = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 smallest_dqs_dly = 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct sdram_params *params = get_sdram_config();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dq_coarse_dly =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].ao.shu[0].selph_dqs0) >> (i << 2)) & 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+ dq_fine_dly =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].ao.shu[0].selph_dqs1) >> (i << 2)) & 0x7;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_dly =</span><br><span style="color: hsl(120, 100%, 40%);">+ (((dq_coarse_dly << 3) + dq_fine_dly) << 5) + params->wr_level[chn][rank][i];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tmp_dly < smallest_dqs_dly)</span><br><span style="color: hsl(120, 100%, 40%);">+ smallest_dqs_dly = tmp_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return smallest_dqs_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_get_dly_range(u8 chn, u8 rank, u8 cal_type, u16 *pre_cal,</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 *begin, s16 *end)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 pre_dq_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cal_type == TX_WIN_MOVE_DQ_DQM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ *begin = dramc_get_smallest_dqs_dly(chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+ *end = *begin + 256;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (cal_type == TX_WIN_MOVE_DQ_ONLY) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pre_dq_dly =</span><br><span style="color: hsl(120, 100%, 40%);">+ (pre_cal[0] > pre_cal[1]) ? pre_cal[1] : pre_cal[0];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pre_dq_dly > 24)</span><br><span style="color: hsl(120, 100%, 40%);">+ pre_dq_dly -= 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ pre_dq_dly = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *begin = pre_dq_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ *end = *begin + 64;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_check_dqs_win(struct dqs_perbit_dly *p,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_step, u8 last_step, u32 fail_bit)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 dqsdly_pass_win, best_pass_win;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (fail_bit == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (p->first_dqsdly_pass == -1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* first DQS pass delay tap */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->first_dqsdly_pass = dly_step;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((p->last_dqsdly_pass == -2) && (dly_step == last_step)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* pass to the last tap */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqsdly_pass = dly_step;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqsdly_pass_win = p->last_dqsdly_pass</span><br><span style="color: hsl(120, 100%, 40%);">+ - p->first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_pass_win = p->best_last_dqsdly_pass</span><br><span style="color: hsl(120, 100%, 40%);">+ - p->best_first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqsdly_pass_win > best_pass_win) {</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_last_dqsdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_first_dqsdly_pass =</span><br><span style="color: hsl(120, 100%, 40%);">+ p->first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* clear to find the next pass range if it has */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->first_dqsdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqsdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((p->first_dqsdly_pass != -1)</span><br><span style="color: hsl(120, 100%, 40%);">+ && (p->last_dqsdly_pass == -2)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqsdly_pass = dly_step - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqsdly_pass_win = p->last_dqsdly_pass</span><br><span style="color: hsl(120, 100%, 40%);">+ - p->first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ best_pass_win = p->best_last_dqsdly_pass</span><br><span style="color: hsl(120, 100%, 40%);">+ - p->best_first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqsdly_pass_win > best_pass_win) {</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_last_dqsdly_pass</span><br><span style="color: hsl(120, 100%, 40%);">+ = p->last_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->best_first_dqsdly_pass</span><br><span style="color: hsl(120, 100%, 40%);">+ = p->first_dqsdly_pass;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* clear to find the next pass range if it has */</span><br><span style="color: hsl(120, 100%, 40%);">+ p->first_dqsdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->last_dqsdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_set_dqdqs_dly(u8 chn, u8 rank, s32 dly)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dly <= 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Hold time calibration */</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rx_dly_factor(chn, rank, RX_DQS, -dly);</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup time calibration */</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rx_dly_factor(chn, rank, RX_DQS, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rx_dly_factor(chn, rank, RX_DQM, dly);</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rx_dly_factor(chn, rank, RX_DQ, dly);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 dramc_rx_window_perbit_cal(u8 chn, u8 cal_type,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rank, u8 engine_type)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 vref;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 vref_begin = 0, vref_end = 1, vref_step = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 vref_scan_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 fail = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i, bit, max_dq_taps;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 index, max_limit;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_step = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 type = cal_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 err_value, fail_bit;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 min_win_size = 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 max_win_size_sum = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ static u32 max_dqsdly_byte[DQS_NUMBER], ave_dqmdly_byte[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ static struct dqs_perbit_dly vref_dq_perbit_dly[DQ_DATA_WIDTH];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dqs_perbit_dly dqdqs_perbit_dly[DQ_DATA_WIDTH];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (engine_type && (rank == RANK_0)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_scan_enable = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_vref_enable(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_scan_enable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("%s [Rank %d] [Channel %d] Calibration Type:%d, engine:%d,vref_enable:%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, rank, chn, type, engine_type, vref_scan_enable);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (engine_type)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_init(chn, rank, DEFAULT_TEST2_1_CAL,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEFAULT_TEST2_2_CAL, TEST_XTALK_PATTERN, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rd_dqc_init(chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_get_vref_range(type, vref_scan_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+ &vref_begin, &vref_end, &vref_step);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* if calibration data is allready stored in emmc,</span><br><span style="color: hsl(120, 100%, 40%);">+ * Vref end need change */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (vref = vref_begin; vref < vref_end; vref += vref_step) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (vref_scan_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_rx_vref(chn, vref);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQ_DATA_WIDTH; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].vref = vref;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].first_dqdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].last_dqdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].first_dqsdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].last_dqsdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].best_first_dqdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].best_last_dqdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].best_first_dqsdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rx_dly_factor(chn, rank, RX_DQM, FIRST_DQ_DELAY);</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rx_dly_factor(chn, rank, RX_DQ, FIRST_DQ_DELAY);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ max_dq_taps = MAX_RX_DQDLY_TAPS;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dly = FIRST_DQS_DELAY; dly < max_dq_taps;</span><br><span style="color: hsl(120, 100%, 40%);">+ dly += dly_step) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_dqdqs_dly(chn, rank, dly);</span><br><span style="color: hsl(120, 100%, 40%);">+ err_value = dram_k_perbit(chn, engine_type);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!vref_scan_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("delay %d ", dly);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (bit = 0; bit < DQ_DATA_WIDTH; bit++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ fail_bit = err_value & ((u32) 1 << bit);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dly < 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_check_dqs_win(</span><br><span style="color: hsl(120, 100%, 40%);">+ &(dqdqs_perbit_dly[bit]),</span><br><span style="color: hsl(120, 100%, 40%);">+ -dly, -FIRST_DQS_DELAY,</span><br><span style="color: hsl(120, 100%, 40%);">+ fail_bit);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_check_dq_win(</span><br><span style="color: hsl(120, 100%, 40%);">+ &(dqdqs_perbit_dly[bit]),</span><br><span style="color: hsl(120, 100%, 40%);">+ dly, max_dq_taps, fail_bit);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!vref_scan_enable) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (fail_bit == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("o");</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("x");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!vref_scan_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg(" [MSB]\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dramk_calcu_best_vref</span><br><span style="color: hsl(120, 100%, 40%);">+ (type | (1 << engine_type), vref_dq_perbit_dly,</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly, min_win_size, max_win_size_sum))</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (engine_type)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_end(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rd_dqc_end(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (vref_scan_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_rx_vref(chn, vref_dq_perbit_dly[0].vref);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ max_dqsdly_byte[i] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ave_dqmdly_byte[i] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQ_DATA_WIDTH; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ index = i / DQS_BIT_NUMBER;</span><br><span style="color: hsl(120, 100%, 40%);">+ fail |= dramc_calcu_best_dly(i,</span><br><span style="color: hsl(120, 100%, 40%);">+ &vref_dq_perbit_dly[i], &max_dqsdly_byte[index]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQ_DATA_WIDTH; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ index = i / DQS_BIT_NUMBER;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set DQS to max for 8-bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dqdqs_perbit_dly[i].best_dqsdly < max_dqsdly_byte[index]) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Delay DQ to compensate extra DQS delay */</span><br><span style="color: hsl(120, 100%, 40%);">+ dly = max_dqsdly_byte[index] -</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dq_perbit_dly[i].best_dqsdly;</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dq_perbit_dly[i].best_dqdly += dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ max_limit = MAX_DQDLY_TAPS - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (vref_dq_perbit_dly[i].best_dqdly > max_limit)</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_dq_perbit_dly[i].best_dqdly = max_limit;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ave_dqmdly_byte[index] += vref_dq_perbit_dly[i].best_dqdly;</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((i + 1) % DQS_BIT_NUMBER == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ ave_dqmdly_byte[index] /= DQS_BIT_NUMBER;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (fail == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("FAIL on perbit_window_cal()\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rx_best_dly_factor(chn, rank, vref_dq_perbit_dly, max_dqsdly_byte,</span><br><span style="color: hsl(120, 100%, 40%);">+ ave_dqmdly_byte);</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_tx_window_perbit_cal(u8 chn, u8 rank, u8 cal_type)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 vref, vref_begin, vref_end, vref_step;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 vref_scan_enable;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 dly_begin = 0, dly_end = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i, bit, index;</span><br><span style="color: hsl(120, 100%, 40%);">+ s16 dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dly_step = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 win_sum;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 err_value, fail_bit;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct per_byte_dly tx_perbyte_dly[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ static u16 dq_precal_result[DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dqs_perbit_dly dqdqs_perbit_dly[DQ_DATA_WIDTH];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dqs_perbit_dly vref_dqdqs_perbit_dly[DQ_DATA_WIDTH];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 min_win_size = 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 max_win_size_sum = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cal_type == TX_WIN_MOVE_DQ_ONLY)</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_scan_enable = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ vref_scan_enable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("%s [Rank %d][Channel %d] Calibration Type:%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, rank, chn, cal_type);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[0], 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[0], 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[1], 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[1], 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << MISC_CTRL1_R_DMAR_FINE_TUNE_DQ_SW_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dqsoscr,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << DQSOSCR_AR_COARSE_TUNE_DQ_SW_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_init(chn, rank, DEFAULT_TEST2_1_CAL, DEFAULT_TEST2_2_CAL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_XTALK_PATTERN, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_get_vref_range(cal_type, vref_scan_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+ &vref_begin, &vref_end, &vref_step);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (vref = vref_begin; vref < vref_end; vref += vref_step) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ win_sum = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQ_DATA_WIDTH; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].vref = vref;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].first_dqdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].last_dqdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].best_first_dqdly_pass = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[i].best_last_dqdly_pass = -2;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (vref_scan_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_tx_vref(chn, rank, vref);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_get_dly_range(chn, rank, cal_type, dq_precal_result,</span><br><span style="color: hsl(120, 100%, 40%);">+ &dly_begin, &dly_end);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("delay range: (%d - %d)\n", dly_begin, dly_end);</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dly = dly_begin; dly < dly_end; dly += dly_step) {</span><br><span style="color: hsl(120, 100%, 40%);">+ set_dly_factor(chn, rank, cal_type, dly);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("delay = %d ", dly);</span><br><span style="color: hsl(120, 100%, 40%);">+ err_value = dram_k_perbit(chn, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (bit = 0; bit < DQ_DATA_WIDTH; bit++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ fail_bit = err_value & ((u32) 1 << bit);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_check_dq_win(&(dqdqs_perbit_dly[bit]),</span><br><span style="color: hsl(120, 100%, 40%);">+ dly, dly_end, fail_bit);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (fail_bit == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("o");</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("x");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg(" [MSB]\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (bit = 0; bit < DQ_DATA_WIDTH; bit++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("dq[%d] win(%d ~ %d)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ bit, dqdqs_perbit_dly[bit].best_first_dqdly_pass,</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly[bit].best_last_dqdly_pass);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramk_calcu_best_vref(cal_type, vref_dqdqs_perbit_dly,</span><br><span style="color: hsl(120, 100%, 40%);">+ dqdqs_perbit_dly, min_win_size, max_win_size_sum);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_end(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("Final Vref is %d\n", vref_dqdqs_perbit_dly[0].vref);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (vref_scan_enable)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_set_tx_vref(chn, rank, vref_dqdqs_perbit_dly[0].vref);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ tx_perbyte_dly[i].min_center = 0xffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ tx_perbyte_dly[i].max_center = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQ_DATA_WIDTH; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ index = i / DQS_BIT_NUMBER;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_calcu_tx_perbyte_dly(i, &vref_dqdqs_perbit_dly[i],</span><br><span style="color: hsl(120, 100%, 40%);">+ &tx_perbyte_dly[index]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < DQS_NUMBER; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ tx_perbyte_dly[i].final_dly =</span><br><span style="color: hsl(120, 100%, 40%);">+ (tx_perbyte_dly[i].max_center +</span><br><span style="color: hsl(120, 100%, 40%);">+ tx_perbyte_dly[i].min_center) >> 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dq_precal_result[i] = tx_perbyte_dly[i].final_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("dq_perbyte_dly[%d] = %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ i, dq_precal_result[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ set_tx_best_dly_factor(chn, rank, tx_perbyte_dly, dq_precal_result);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_read_dbi_onoff(u8 onoff)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DRAMC Read-DBI On/Off */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ (onoff << SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ (onoff << SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_write_dbi_onoff(u8 onoff)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1value, chn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DRAMC Write-DBI On/Off */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].wodt,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1 << SHU1_WODT_DBIWR_SHIFT,</span><br><span style="color: hsl(120, 100%, 40%);">+ (onoff << SHU1_WODT_DBIWR_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u1value = read32(&ch[0].ao.shu[0].wodt);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("DRAMC Write-DBI On/Off = %d\n", u1value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u8 dramc_zq_calibration(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4Response;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4TimeCnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *u4RegBackup[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.dramc_pd_ctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ &ch[chn].ao.ckectrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[%s] rank:%d\n", __func__, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+ u4TimeCnt = TIME_OUT_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_restore_multi_reg(SAVE_VALUE,</span><br><span style="color: hsl(120, 100%, 40%);">+ u4RegBackup, ARRAY_SIZE(u4RegBackup));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cke_fix_onoff(CKE_FIXON, chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.mrs,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MPCRK_MASK, (rank << MRS_MPCRK_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.mpc_option,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << MPC_OPTION_MPCRKEN_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, (0x1 << SPCMD_ZQCEN_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ u4Response =</span><br><span style="color: hsl(120, 100%, 40%);">+ (read32(&ch[chn].nao.spcmdresp) &</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << SPCMDRESP_ZQC_RESPONSE_SHIFT)) >></span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMDRESP_ZQC_RESPONSE_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u4TimeCnt--;</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("try:%d\n", u4TimeCnt);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while ((u4Response == 0) && (u4TimeCnt > 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (u4TimeCnt == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("ZQCAL Start fail (time out)\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd, (0x1 << SPCMD_ZQCEN_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ u4TimeCnt = TIME_OUT_CNT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmd, (0x1 << SPCMD_ZQLATEN_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ u4Response = (read32(&ch[chn].nao.spcmdresp) &</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << SPCMDRESP_ZQLAT_RESPONSE_SHIFT)) >></span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMDRESP_ZQLAT_RESPONSE_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ u4TimeCnt--;</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("%d\n", u4TimeCnt);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while ((u4Response == 0) && (u4TimeCnt > 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (u4TimeCnt == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("ZQCAL Latch fail (time out)\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.spcmd, (0x1 << SPCMD_ZQLATEN_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ save_restore_multi_reg(RESTORE_VALUE,</span><br><span style="color: hsl(120, 100%, 40%);">+ u4RegBackup, ARRAY_SIZE(u4RegBackup));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dle_factor_handler(u8 chn, u8 curr_val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (curr_val < 2)</span><br><span style="color: hsl(120, 100%, 40%);">+ curr_val = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shu[0].conf[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (SHU_CONF1_DATLAT_MASK) | (SHU_CONF1_DATLAT_DSEL_MASK) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (SHU_CONF1_DATLAT_DSEL_PHY_MASK),</span><br><span style="color: hsl(120, 100%, 40%);">+ (curr_val << SHU_CONF1_DATLAT_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((curr_val - 2) << SHU_CONF1_DATLAT_DSEL_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((curr_val - 2) << SHU_CONF1_DATLAT_DSEL_PHY_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_phy_reset(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u32 rx_datlat_result(u8 chn, u8 rank, u8 type, u8 best_step)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static u8 aru1RxDatlatResult[CHANNEL_NUM][RANK_MAX] = {0x0};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (type == SAVE_VALUE) {</span><br><span style="color: hsl(120, 100%, 40%);">+ aru1RxDatlatResult[chn][rank] = best_step;</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return aru1RxDatlatResult[chn][rank];</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 dramc_rxdatlat_scan(u8 chn, u8 rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ enum dram_datlat_type use_rxtx_scan)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ii;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4prv_register_080;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 u4err_value = 0xffffffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ucfirst, ucbegin, ucsum, ucbest_step;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 u2DatlatBegin;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("[DATLAT]\nCH%d RK%d, use_rxtx_scan=%d\n\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ chn, rank, use_rxtx_scan);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u4prv_register_080 = read32(&ch[chn].ao.shu[0].conf[1]);</span><br><span style="color: hsl(120, 100%, 40%);">+ ucbest_step = (u8) (read32(&ch[chn].ao.shu[0].conf[1])</span><br><span style="color: hsl(120, 100%, 40%);">+ & (SHU_CONF1_DATLAT_MASK));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("DATLAT Default: 0x%x\n", ucbest_step);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ucfirst = 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+ ucbegin = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ ucsum = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_init(chn, rank, DEFAULT_TEST2_1_CAL, DEFAULT_TEST2_2_CAL,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_XTALK_PATTERN, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u2DatlatBegin = 7;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (ii = u2DatlatBegin; ii < DATLAT_TAP_NUMBER; ii++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dle_factor_handler(chn, ii);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (use_rxtx_scan == DATLAT_USE_DEFAULT) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u4err_value =</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_run(chn,</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_WRITE_READ_CHECK,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_XTALK_PATTERN);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (u4err_value == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ucbegin == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ucfirst = ii;</span><br><span style="color: hsl(120, 100%, 40%);">+ ucbegin = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ucbegin == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ ucsum++;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ucsum > 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ucbegin == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+ ucbegin = 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("TAP=%2d, err_value=0x%8x, sum=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ ii, u4err_value, ucsum);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_engine2_end(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ucsum == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("no DATLAT taps pass, DATLAT calibration fail!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (ucsum <= 3)</span><br><span style="color: hsl(120, 100%, 40%);">+ ucbest_step = ucfirst + (ucsum >> 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ ucbest_step = ucfirst + 2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rx_datlat_result(chn, rank, SAVE_VALUE, ucbest_step);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("pattern=%d first_step=%d total pass=%d best_step=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_XTALK_PATTERN, ucfirst, ucsum, ucbest_step);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ucsum < 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[NOTICE] CH%d, DatlatSum %d\n", chn, ucsum);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ucsum == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("DATLAT calibration fail,"</span><br><span style="color: hsl(120, 100%, 40%);">+ "write back to default values!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.shu[0].conf[1], u4prv_register_080);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ dle_factor_handler(chn, ucbest_step);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.padctrl, (PADCTRL_DQIENQKEND_MASK),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << PADCTRL_DQIENQKEND_SHIFT) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << PADCTRL_DQIENLATEBEGIN_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ return ucsum;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_datlat_cal(u8 chn, u8 rank)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1DatlatWindowSum;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u1DatlatWindowSum = dramc_rxdatlat_scan(chn, rank, DATLAT_USE_DEFAULT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_dual_rank_rx_datlat_cal(u8 chn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1FinalDatlat, u1Datlat0, u1Datlat1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u1Datlat0 = rx_datlat_result(chn, RANK_0, RESTORE_VALUE, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ u1Datlat1 = rx_datlat_result(chn, RANK_1, RESTORE_VALUE, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (u1Datlat0 > u1Datlat1)</span><br><span style="color: hsl(120, 100%, 40%);">+ u1FinalDatlat = u1Datlat0;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ u1FinalDatlat = u1Datlat1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dle_factor_handler(chn, u1FinalDatlat);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[%s] RK0: %d, RK1: %d, Final_Datlat %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__, u1Datlat0, u1Datlat1, u1FinalDatlat);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void imp_cal_vref_sel(u8 term_option, u8 u1ImpCalStage)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1RegTmpValue = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (term_option == 1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u1RegTmpValue = IMP_LP4X_TERM_VREF_SEL;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (u1ImpCalStage == IMPCAL_STAGE_DRVP)</span><br><span style="color: hsl(120, 100%, 40%);">+ u1RegTmpValue = IMP_DRVP_LP4X_UNTERM_VREF_SEL;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (u1ImpCalStage == IMPCAL_STAGE_DRVN)</span><br><span style="color: hsl(120, 100%, 40%);">+ u1RegTmpValue = IMP_DRVN_LP4X_UNTERM_VREF_SEL;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ u1RegTmpValue = IMP_TRACK_LP4X_UNTERM_VREF_SEL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dbg("[%s] IMP_VREF_SEL 0x%x\n", __func__, u1RegTmpValue);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x3f << 8, u1RegTmpValue << 8);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_sw_impedance_save_register(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int tmp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 broadcast_bak;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 term_opt, ca_term_option = 0, dq_term_option = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 uSwImpedanceResult[2][4] = { {0}, {0} };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[0][0] = params->impedance[ca_term_option][0];</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[0][1] = params->impedance[ca_term_option][1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[0][2] = params->impedance[ca_term_option][2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[0][3] = params->impedance[ca_term_option][3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[1][0] = params->impedance[dq_term_option][0];</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[1][1] = params->impedance[dq_term_option][1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[1][2] = params->impedance[dq_term_option][2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[1][3] = params->impedance[dq_term_option][3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ broadcast_bak = get_dramc_broadcast();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[ODT_OFF][2] = uSwImpedanceResult[ODT_ON][2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[ODT_OFF][3] = uSwImpedanceResult[ODT_ON][3];</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF, tmp);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set IMP_VREF_SEL value for DRVP */</span><br><span style="color: hsl(120, 100%, 40%);">+ imp_cal_vref_sel(dq_term_option, IMPCAL_STAGE_DRVP);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1F << 5)|(0x1F << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][0] << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][1] << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1F << 25)|(0x1F << 20) | (1 << 31),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][0] << 25) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][1] << 20) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (!dq_term_option << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1F << 5)|(0x1F << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][2] << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][3] << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1F << 25)|(0x1F << 20),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][2] << 25) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][3] << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DQS */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1F << 25)|(0x1F << 20),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][0] << 25) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][1] << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1F << 15)|(0x1F << 10),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][0] << 15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][1] << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1F << 25)|(0x1F << 20),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][2] << 25) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][3] << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1F << 15)|(0x1F << 10),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][2] << 15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[dq_term_option][3] << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CMD & CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[1], (0x1F << 15)|(0x1F << 10),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][0] << 15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][1] << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[1], (0x1F << 5)|(0x1F << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][0] << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][1] << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1F << 15)|(0x1F << 10),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][2] << 15) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][3] << 10));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1F << 5)|(0x1F << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][2] << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][3] << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* RG_TX_*RCKE_DRVP/RG_TX_*RCKE_DRVN doesn't set, so set 0xA first */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], (0x1f << 17),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][0] << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], (0x1f << 22),</span><br><span style="color: hsl(120, 100%, 40%);">+ (uSwImpedanceResult[ca_term_option][1] << 22));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DRVP[4:0] = RG_TX_ARCMD_PU_PRE<1:0>, RG_TX_ARCLK_DRVN_PRE<2:0> */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ (((8 >> 3) & 0x3) <<</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((8 & 0x7) << SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_SHIFT));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1F << 16), (0x9 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1F << 16), (0x9 << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (term_opt = 0; term_opt < 2; term_opt++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("term_opt=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ term_opt, uSwImpedanceResult[term_opt][0],</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[term_opt][1],</span><br><span style="color: hsl(120, 100%, 40%);">+ uSwImpedanceResult[term_opt][3]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(broadcast_bak);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dramc_phy_dcm_2_channel(u8 chn, u8 bEn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 shu, shu_cnt = DRAM_DFS_SHUFFLE_MAX;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!bEn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 20) | (0x1 << 19) | 0x3FF << 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 20) | (0x1 << 19) | 0x3FF << 8);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = DRAM_DFS_SHUFFLE_1; shu < shu_cnt; shu++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[0].dq[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1FFF << 19);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[1].dq[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1FFF << 19);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[shu].ca_cmd[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1FFF << 19);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.misc_cg_ctrl5,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 16) | (0x7 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void enable_dramc_phy_dcm(u8 bEn)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 broadcast_bak = get_dramc_broadcast();</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 shu, shu_cnt = DRAM_DFS_SHUFFLE_MAX;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM ; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], (0x1 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], (0x1 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], (0x1 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < shu_cnt; shu++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[0].dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[1].dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].ca_dll[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bEn) { /* DCM on */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 26) | (0x1 << 30) | (0x1 << 31),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 5) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 26) | (0x1 << 30) | (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CHANNEL_EMI free run */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x806003BE);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x806003BF);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x806003BF);</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.misc_ctrl3, (0x3 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < shu_cnt; shu++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.shu[shu].ca_cmd[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5) | (0x1 << 26) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 30) | (0x1 << 31),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 0) | (0x0 << 1) | (0x0 << 2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 5) | (0x1 << 26) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0 << 30) | (0x0 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* mem_dcm */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060037E);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060037F);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060037E);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl3, (0x3 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shu = 0; shu < shu_cnt; shu++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[shu].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[shu].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[shu].ca_cmd[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_dramc_phy_dcm_2_channel(chn, bEn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(broadcast_bak);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void reset_delay_chain_before_calibration(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn = 0, rank = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (rank = 0; rank < RANK_MAX; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xffffff << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xfffffff << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[0],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xfffffff << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[1],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0xf << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_hw_gating_onoff(u8 chn, u8 u1OnOff)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.shuctrl2, (0x3 << 14),</span><br><span style="color: hsl(120, 100%, 40%);">+ (u1OnOff << 14) | (u1OnOff << 15));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal2, (0x1 << 28), (u1OnOff << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal, (0x1 << 24), (u1OnOff << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].ao.stbcal, (0x1 << 22), (u1OnOff << 22));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_rx_input_delay_tracking_init_by_freq(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u1DVS_Delay;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u1DVS_Delay = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 20), (u1DVS_Delay << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[5],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x7 << 20), (u1DVS_Delay << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 12) | (0x1 << 13), (0x0 << 12) | (0x0 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[7],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 12) | (0x1 << 13), (0x0 << 12) | (0x0 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void apply_config_before_calibration(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 shuf = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clk free run */</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_dramc_phy_dcm(0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set LP4 Rank0/1 CA/TX delay chain to 0</span><br><span style="color: hsl(120, 100%, 40%);">+ * CA0~9 per bit delay line -> CHA_CA0 CHA_CA3 CHA_B0_DQ6 CHA_B0_DQ7</span><br><span style="color: hsl(120, 100%, 40%);">+ * CHA_B0_DQ2 CHA_B0_DQ5 CHA_B0_DQ4 CHA_B0_DQ1 CHA_B0_DQ0 CHA_B0_DQ3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ reset_delay_chain_before_calibration();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MR4 refresh cnt set to 0x1ff (2ms update) */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].conf[3],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1ff << 16), (0x1ff << 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The counter for Read MR4 cannot be reset</span><br><span style="color: hsl(120, 100%, 40%);">+ * after SREF if DRAMC no power down. */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ---- ZQ CS init -------- */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ZQ Calibration Time, unit: 38.46ns, tZQCAL min is 1 us.</span><br><span style="color: hsl(120, 100%, 40%);">+ * need to set larger than 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.shu[0].scintv,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 1), (0x1b << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Every refresh number to issue ZQCS commands,</span><br><span style="color: hsl(120, 100%, 40%);">+ * only for DDR3/LPDDR2/LPDDR3/LPDDR4</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shuf = DRAM_DFS_SHUFFLE_1; shuf < DRAM_DFS_SHUFFLE_MAX; shuf++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].ao.shu[shuf].conf[3], (0x1ff << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* HW send ZQ command for both rank, disable it due to</span><br><span style="color: hsl(120, 100%, 40%);">+ * some dram only have 1 ZQ pin for two rank.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dramctrl, (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable LP4 HW ZQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ZQCSDISB=0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LP4 ZQCALDISB=0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ /* End of ZQ CS init */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CBT_MODE = NORMAL_MODE */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dqsoscr, (0x1 << 26));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].ao.dqsoscr, (0x1 << 25));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Recover write-DBI of DRAMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_write_dbi_onoff(DBI_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_read_dbi_onoff(DBI_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* disable MR4 read, REFRDIS=1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.spcmdctrl, (0x1 << 29));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dqsoscr, (0x1 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ for (shuf = 0; shuf < DRAM_DFS_SHUFFLE_MAX; shuf++)</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.shu[shuf].scintv,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable HW gating tracking first, 0x1c0[31],</span><br><span style="color: hsl(120, 100%, 40%);">+ * need to disable both coarse tune and fine tune tracking</span><br><span style="color: hsl(120, 100%, 40%);">+ * or the gating delay reg won't be valid.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_hw_gating_onoff(chn, GATING_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable gating debug */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.stbcal2, (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t r = 0; r < 2; r++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t b = 0; b < 2; b++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable RX delay tracking */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 28));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 23));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* RX delay mux, delay vlaue from reg. */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.r0_ca_rxdvs[2],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 30));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].phy.misc_ctrl1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 7) | (0x1 << 11));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set to all-bank refresh */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.refctrl0, (0x1 << 18));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set MPCRK to 0, MPCRKEN alwasys set 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.mrs, (0x3 << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.mpc_option, (0x1 << 17));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* RG mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[0].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0), (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.b[1].dq[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0), (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[chn].phy.ca_cmd[6],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x3 << 0), (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_input_delay_tracking_init_by_freq();</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 25));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[chn].ao.drsctrl, (0x1 << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dram_calibration_all_channel(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (u8 rank = RANK_0; rank < RANK_MAX; rank++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("start K ch:%d, rank:%d\n", chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_zq_calibration(chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+ auto_refresh_switch(chn, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cmd_bus_training(chn, rank, params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Dram will be reset when finish write leveling */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_write_leveling(chn, rank, params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ auto_refresh_switch(chn, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_dqs_gating_cal(chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_window_perbit_cal(chn, RX_WIN, rank, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_tx_window_perbit_cal(chn, rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_WIN_MOVE_DQ_DQM);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_tx_window_perbit_cal(chn, rank,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_WIN_MOVE_DQ_ONLY);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_datlat_cal(chn, rank);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_window_perbit_cal(chn, RX_WIN, rank, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ENABLE_TX_TRACKING */</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_rx_dqs_gating_post_process(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_dual_rank_rx_datlat_cal(chn);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c</span><br><span>index e37fd56..8ef1613 100644</span><br><span>--- a/src/soc/mediatek/mt8183/emi.c</span><br><span>+++ b/src/soc/mediatek/mt8183/emi.c</span><br><span>@@ -13,9 +13,312 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_pi_api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_register.h></span><br><span> #include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/infracfg.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/spm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct emi_regs *emi_regs = (void *)EMI_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void get_dram_rank_size(u64 *dram_rank_size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 col_bit, row_bit;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 shift_for_16bit = 1; /* data width = 2 bytes */</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ch0_rank0_size, ch0_rank1_size, ch1_rank0_size, ch1_rank1_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ch_rank0_size = 0, ch_rank1_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_cona = read32(&emi_regs->cona);</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 emi_conh = read32(&emi_regs->conh);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (emi_cona & 0x2)</span><br><span style="color: hsl(120, 100%, 40%);">+ shift_for_16bit = 0; /* data width = 4 bytes */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[0] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[1] = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ch0_rank0_size = (emi_conh >> 16) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+ ch0_rank1_size = (emi_conh >> 20) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+ ch1_rank0_size = (emi_conh >> 24) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+ ch1_rank1_size = (emi_conh >> 28) & 0xf;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CH0 EMI */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ch0_rank0_size == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* rank 0 setting */</span><br><span style="color: hsl(120, 100%, 40%);">+ col_bit = ((emi_cona >> 4) & 0x03) + 9;</span><br><span style="color: hsl(120, 100%, 40%);">+ row_bit = ((((emi_cona >> 24) & 0x01) << 2) +</span><br><span style="color: hsl(120, 100%, 40%);">+ ((emi_cona >> 12) & 0x03)) + 13;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* data width (bytes) * 8 banks */</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank0_size = ((u64)(1 << (row_bit + col_bit))) *</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u64)(4 >> shift_for_16bit) * 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank0_size = (ch0_rank0_size * 256 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* dual rank enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (0 != (emi_cona & (1 << 17))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ch0_rank1_size == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ col_bit = ((emi_cona >> 6) & 0x03) + 9;</span><br><span style="color: hsl(120, 100%, 40%);">+ row_bit = ((((emi_cona >> 25) & 0x01) << 2) +</span><br><span style="color: hsl(120, 100%, 40%);">+ ((emi_cona >> 14) & 0x03)) + 13;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* data width (bytes) * 8 banks */</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank1_size = ((u64)(1 << (row_bit + col_bit))) *</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u64)(4 >> shift_for_16bit) * 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank1_size = (ch0_rank1_size * 256 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[0] = ch_rank0_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[1] = ch_rank1_size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ch1_rank0_size == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* rank0 setting */</span><br><span style="color: hsl(120, 100%, 40%);">+ col_bit = ((emi_cona >> 20) & 0x03) + 9;</span><br><span style="color: hsl(120, 100%, 40%);">+ row_bit = ((((emi_conh >> 4) & 0x01) << 2) +</span><br><span style="color: hsl(120, 100%, 40%);">+ ((emi_cona >> 28) & 0x03)) + 13;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* data width (bytes) * 8 banks */</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank0_size = ((u64)(1 << (row_bit + col_bit))) *</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u64)(4 >> shift_for_16bit) * 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank0_size = (ch1_rank0_size * 256 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (0 != (emi_cona & (1 << 16))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ch1_rank1_size == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ col_bit = ((emi_cona >> 22) & 0x03) + 9;</span><br><span style="color: hsl(120, 100%, 40%);">+ row_bit = ((((emi_conh >> 5) & 0x01) << 2) +</span><br><span style="color: hsl(120, 100%, 40%);">+ ((emi_cona >> 30) & 0x03)) + 13;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* data width (bytes) * 8 banks */</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank1_size = ((u64)(1 << (row_bit + col_bit))) *</span><br><span style="color: hsl(120, 100%, 40%);">+ ((u64)(4 >> shift_for_16bit) * 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ ch_rank1_size = (ch1_rank1_size * 256 << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[0] += ch_rank0_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_rank_size[1] += ch_rank1_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> size_t sdram_size(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return (size_t)4 * GiB;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t dram_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rank_size[RANK_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_dram_rank_size(&rank_size[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int i = 0; i < RANK_MAX; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_size += rank_size[i];</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_show("rank%d size:0x%llx\n", i, rank_size[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return dram_size;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_rank_info_to_conf(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 u4value = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CONA 17th bit 0: Disable dual rank mode</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1: Enable dual rank mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ u4value = ((params->EMI_CONA_VAL & (0x1 << 17)) >> 17) ? 0 : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 12, u4value << 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_MRR_pinmux_mapping(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 chn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 phy_mapping[CHANNEL_NUM][16] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ [CHANNEL_A] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, 0, 2, 4, 3, 7, 5, 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ 9, 8, 12, 11, 10, 15, 13, 14</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ [CHANNEL_B] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, 1, 5, 6, 3, 7, 4, 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ 9, 8, 12, 15, 11, 14, 13, 10</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (chn = 0; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *map = phy_mapping[chn];</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.mrr_bit_mux1,</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[0] << 0) | (map[1] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[2] << 16) | (map[3] << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.mrr_bit_mux2,</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[4] << 0) | (map[5]<<8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[6] << 16) | (map[7] << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.mrr_bit_mux3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[8] << 0) | (map[9] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[10] << 16) | (map[11]<<24));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].ao.mrr_bit_mux4,</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[12] << 0) | (map[13] << 8) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (map[14] << 16) | (map[15] << 24));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void global_option_init(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ set_rank_info_to_conf(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ set_MRR_pinmux_mapping();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void emi_esl_setting1(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cona, 0xa053a154);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conb, 0x17283544);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conc, 0x0a1a0b1a);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cond, 0x3657587a);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cone, 0x80400148);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conf, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cong, 0x2b2b2a38);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conh, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->coni, 0x00008803);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conm, 0x000001ff);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conn, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->mdct, 0x11338c17);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->mdct_2nd, 0x00001112);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->iocl, 0xa8a8a8a8);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->iocl_2nd, 0x25252525);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->iocm, 0xa8a8a8a8);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->iocm_2nd, 0x25252525);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->testb, 0x00060037);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->testc, 0x38460000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->testd, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arba, 0x4020524f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbb, 0x4020504f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbc, 0xa0a050c6);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbd, 0x000070cc);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbe, 0x40406045);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbf, 0xa0a070d5);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbg, 0xa0a0504f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbh, 0xa0a0504f);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbi, 0x00007108);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->arbi_2nd, 0x00007108);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->slct, 0x0001ff00);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_cona, 0x0400a051);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_conb, 0x00ff2048);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_conc, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_mdct, 0x88008817);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_testb, 0x00030027);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_testc, 0x38460002);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_testd, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_md_pre_mask, 0x00000f00);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_md_pre_mask_shf, 0x00000b00);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbi, 0x20406188);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbi_2nd, 0x20406188);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbj, 0x3719595e);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbj_2nd, 0x3719595e);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbk, 0x64f3fc79);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arbk_2nd, 0x64f3fc79);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_slct, 0x00080888);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_arb_ref, 0x82410222);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_emi_shf0, 0x8a228c17);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_rkarb0, 0x0006002f);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_rkarb1, 0x01010101);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_rkarb2, 0x10100820);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_eco3, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void emi_esl_setting2(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[0].emi.chn_conc, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conm, 0x05ff);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_OFF);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void emi_init(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ emi_esl_setting1();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->cona, params->EMI_CONA_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conf, params->EMI_CONF_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->conh, params->EMI_CONH_VAL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (size_t chn = CHANNEL_A; chn < CHANNEL_NUM; chn++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].emi.chn_cona, params->CHN_EMI_CONA_VAL[chn]);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&ch[chn].emi.chn_conc, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void emi_init2(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ emi_esl_setting2();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 1, 0x1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 7, 0x1 << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0, 0x0A000705);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0_3rd, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* EMI QoS 0.5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0_2nd, 0x00030023);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0_4th, 0x00c00023);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(&emi_regs->bwct0_5th, 0x00240023);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dramc_init_pre_settings(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32(&ch[0].phy.ca_cmd[8],</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 21) | (0x1 << 20) | (0x1 << 19) | (0x1 << 18) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1F << 8) | (0x1f << 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1 << 19) | (0xa << 8) | (0xa << 0));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 12));</span><br><span style="color: hsl(120, 100%, 40%);">+ clrbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 13));</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 31));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void init_dram(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ global_option_init(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ emi_init(params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_broadcast_onoff(DRAMC_BROADCAST_ON);</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_init_pre_settings();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_sw_impedance_save_register(params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_init(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ emi_init2(params);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void do_calib(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ apply_config_before_calibration();</span><br><span style="color: hsl(120, 100%, 40%);">+ dram_calibration_all_channel(params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_ac_timing_optimize();</span><br><span style="color: hsl(120, 100%, 40%);">+ dramc_runtime_config();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_set_emi(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ init_dram(params);</span><br><span style="color: hsl(120, 100%, 40%);">+ do_calib(params);</span><br><span> }</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>index de7eb1f..f8edf5b 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h</span><br><span>@@ -19,7 +19,6 @@</span><br><span> enum {</span><br><span> MCUCFG_BASE = 0x0C530000,</span><br><span> IO_PHYS = 0x10000000,</span><br><span style="color: hsl(0, 100%, 40%);">- DDR_BASE = 0x40000000</span><br><span> };</span><br><span> </span><br><span> enum {</span><br><span>@@ -30,6 +29,9 @@</span><br><span> RGU_BASE = IO_PHYS + 0x00007000,</span><br><span> GPT_BASE = IO_PHYS + 0x00008000,</span><br><span> APMIXED_BASE = IO_PHYS + 0x0000C000,</span><br><span style="color: hsl(120, 100%, 40%);">+ EMI_BASE = IO_PHYS + 0x00219000,</span><br><span style="color: hsl(120, 100%, 40%);">+ EMI_MPU_BASE = IO_PHYS + 0x00226000,</span><br><span style="color: hsl(120, 100%, 40%);">+ DRAMC_CH_BASE = IO_PHYS + 0x00228000,</span><br><span> UART0_BASE = IO_PHYS + 0x01002000,</span><br><span> SPI0_BASE = IO_PHYS + 0x0100A000,</span><br><span> SPI1_BASE = IO_PHYS + 0x01010000,</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h</span><br><span>new file mode 100644</span><br><span>index 0000000..08b7b78</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h</span><br><span>@@ -0,0 +1,54 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _DRAMC_COMMON_MT8183_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _DRAMC_COMMON_MT8183_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_A = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_B,</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_NUM</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RANK_0 = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ RANK_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ RANK_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum dram_odt_type {</span><br><span style="color: hsl(120, 100%, 40%);">+ ODT_OFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ ODT_ON</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DQ_DATA_WIDTH = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_BIT_NUMBER = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER)</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Internal CBT mode enum</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1. Calibration flow uses vGet_Dram_CBT_Mode to</span><br><span style="color: hsl(120, 100%, 40%);">+ * differentiate between mixed vs non-mixed LP4</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2. Declared as dram_cbt_mode[RANK_MAX] internally to</span><br><span style="color: hsl(120, 100%, 40%);">+ * store each rank's CBT mode type</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CBT_NORMAL_MODE = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ CBT_BYTE_MODE1</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _DRAMC_COMMON_MT8183_H_ */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>new file mode 100644</span><br><span>index 0000000..409086f</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h</span><br><span>@@ -0,0 +1,245 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _DRAMC_PI_API_MT8183_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _DRAMC_PI_API_MT8183_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define dramc_show(_x_...) printk(BIOS_INFO, _x_)</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_DEBUG_DRAM)</span><br><span style="color: hsl(120, 100%, 40%);">+#define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define dramc_dbg(_x_...)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DISABLE 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DATLAT_TAP_NUMBER 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_TEST2_1_CAL 0x55000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEFAULT_TEST2_2_CAL 0xaa000400</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_CMP_CPT_WAIT_LOOP 10000</span><br><span style="color: hsl(120, 100%, 40%);">+#define TIME_OUT_CNT 100</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DRAMC_BROADCAST_ON 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define DRAMC_BROADCAST_OFF 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define MR13_RRO 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define POS_BANK_NUM 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_BACKUP_REG_CNT 64</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_ISI_PATTERN = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_AUDIO_PATTERN,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_XTALK_PATTERN,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_TA1_SIMPLE,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_TESTPAT4,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_TESTPAT4_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_MIX_PATTERN,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST_DMA,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum dram_datlat_type {</span><br><span style="color: hsl(120, 100%, 40%);">+ DATLAT_USE_DEFAULT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ DATLAT_USE_RX_SCAN,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum dram_te_op {</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_WRITE_READ_CHECK = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TE_OP_READ_CHECK</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DBI_OFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ DBI_ON</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_0 = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_1,</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DLL_MASTER_CH = CHANNEL_A,</span><br><span style="color: hsl(120, 100%, 40%);">+ DLL_SLAVE_CH = CHANNEL_B,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQ_DQS_MOVE_DQ_ONLY = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQ_DQS_MOVE_DQM_ONLY,</span><br><span style="color: hsl(120, 100%, 40%);">+ TX_DQ_DQS_MOVE_DQ_DQM</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_CA_FINE_TUNE_DELAY = 63,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_CS_FINE_TUNE_DELAY = 63,</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_CLK_FINE_TUNE_DELAY = 31,</span><br><span style="color: hsl(120, 100%, 40%);">+ CATRAINING_NUM = 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ PASS_RANGE_NA = 0x7fff</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CBT_LOW_FREQ = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ CBT_HIGH_FREQ = 1</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CBT_OFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ CBT_ON = 1</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ GATING_OFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ GATING_ON = 1</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ CKE_FIXOFF = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ CKE_FIXON,</span><br><span style="color: hsl(120, 100%, 40%);">+ CKE_DYNAMIC</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RANK_SINGLE = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ RANK_DUAL</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ GATING_PATTERN_NUM = 0x23,</span><br><span style="color: hsl(120, 100%, 40%);">+ GATING_GOLDEND_DQSCNT = 0x4646</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPCAL_STAGE_DRVP = 0x1,</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPCAL_STAGE_DRVN,</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPCAL_STAGE_TRACKING,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_COARSE_STEP = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_FINE_START = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_FINE_END = 32,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_FINE_STEP = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ DQS_GW_FREQ_DIV = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_DQS_CTL_LOOP = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ RX_DLY_DQSIENSTB_LOOP = 32</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DRAM_DFS_SHUFFLE_1 = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ DRAM_DFS_SHUFFLE_2,</span><br><span style="color: hsl(120, 100%, 40%);">+ DRAM_DFS_SHUFFLE_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ DRAM_DFS_SHUFFLE_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TYPE_DDR1 = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ TYPE_LPDDR2,</span><br><span style="color: hsl(120, 100%, 40%);">+ TYPE_LPDDR3,</span><br><span style="color: hsl(120, 100%, 40%);">+ TYPE_PCDDR3,</span><br><span style="color: hsl(120, 100%, 40%);">+ TYPE_LPDDR4,</span><br><span style="color: hsl(120, 100%, 40%);">+ TYPE_LPDDR4X,</span><br><span style="color: hsl(120, 100%, 40%);">+ TYPE_LPDDR4P</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_DRAM_TYPE = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_FREQUENCY,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_DBI_ONOFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_BYTE_MODE,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRAS,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRP,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRPAB,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRC,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRFC,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRFCPB,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TXP,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRTP,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRCD,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TWR,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TWTR,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRRD,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TFAW,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRTW_ODT_OFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRTW_ODT_ON,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_REFCNT,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_REFCNT_FR_CLK,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TXREFCNT,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TZQCS,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRTPD,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TWTPD,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TMRR2W_ODT_OFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TMRR2W_ODT_ON,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRAS_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRP_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRPAB_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRC_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRFC_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRFCPB_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TXP_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRTP_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRCD_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TWR_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TWTR_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRRD_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TFAW_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRTW_05T_ODT_OFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRTW_05T_ODT_ON,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TRTPD_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_TWTPD_05T,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_XRTW2W,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_XRTW2R,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_XRTR2W,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_XRTR2R,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_DMCATRAIN_INTV,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_DQSINCTL_FOR_GATING,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_DATLAT,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_MODE_REG_WL,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_MODE_REG_RL,</span><br><span style="color: hsl(120, 100%, 40%);">+ AC_TIMING_ITEM_NUM</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SAVE_VALUE,</span><br><span style="color: hsl(120, 100%, 40%);">+ RESTORE_VALUE</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_init(const struct sdram_params *params);</span><br><span style="color: hsl(120, 100%, 40%);">+void get_dram_rank_size(u64 *dram_rank_size);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_runtime_config(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void dram_calibration_all_channel(const struct sdram_params *params);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_engine2_init(u8 chn, u8 u1RankSel, u32 test2_1, u32 test2_2,</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 testaudpat, u8 log2loopcount);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 dramc_engine2_run(u8 chn, enum dram_te_op wr, u8 testaudpat);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_engine2_end(u8 chn);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_sw_impedance_save_register(const struct sdram_params *params);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_broadcast_onoff(u32 bOnOff);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 get_dramc_broadcast(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void apply_config_before_calibration(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_gating_mode(u8 chn, u8 mode);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_hw_gating_onoff(u8 chn, u8 u1OnOff);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_ac_timing_optimize(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void cke_fix_onoff(int option, u8 chn);</span><br><span style="color: hsl(120, 100%, 40%);">+void save_restore_multi_reg(u8 type, u32 **reg_addr, u32 reg_count);</span><br><span style="color: hsl(120, 100%, 40%);">+u8 dramc_zq_calibration(u8 chn, u8 rank);</span><br><span style="color: hsl(120, 100%, 40%);">+void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value);</span><br><span style="color: hsl(120, 100%, 40%);">+void enable_dramc_phy_dcm(u8 bEn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _DRAMC_PI_API_MT8183_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h</span><br><span>new file mode 100644</span><br><span>index 0000000..9ebb5e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h</span><br><span>@@ -0,0 +1,1446 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _DRAMC_REGISTER_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _DRAMC_REGISTER_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_no_regs_rk_counter {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pre_standby_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pre_powerdown_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t act_standby_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t act_powerdown_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_nao_regs_rk {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsosc_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsosc_delta;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsosc_delta2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_1[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t current_tx_setting1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t current_tx_setting2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t current_tx_setting3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t current_tx_setting4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dummy_rd_data[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t b0_stb_max_min_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t b1_stb_max_min_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t b2_stb_max_min_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t b3_stb_max_min_dly;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsiendly;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsienuidly;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsienuidly_p1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_2[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs_stbcaldec_cnt1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs_stbcaldec_cnt2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs_stbcalinc_cnt1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs_stbcalinc_cnt2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t fine_tune_dq_cal;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsg_retry_flag;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t fine_tune_dqm_cal;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs0_stbcal_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs1_stbcal_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs2_stbcal_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs3_stbcal_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t b01_stb_dbg_info[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t b23_stb_dbg_info[16];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_nao_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t testmode;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lbwdat0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lbwdat1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lbwdat2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lbwdat3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved0[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ckphchk;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dmmonitor;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved1[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t testchip_dma1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved2[19];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_statusa;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t special_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spcmdresp;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrr_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrr_status2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrrdata0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrrdata1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrrdata2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrrdata3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t drs_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved4[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t jmeter_st;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tcmdo1lat;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rdqc_cmp;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ckphchk_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved5[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hwmrr_push2pop_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hwmrr_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hw_refrate_mon;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved6[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t testrpt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cmp_err;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test_abit_status1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test_abit_status2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test_abit_status3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test_abit_status4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved7[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsdly0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq_cal_max[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs_cal_min[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs_cal_max[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqical0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqical1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqical2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqical3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved8[15];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t testchip_dma_status[34];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved9[30];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t refresh_pop_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t freerun_26m_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dramc_idle_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t r2r_page_hit_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t r2r_page_miss_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t r2r_interbank_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t r2w_page_hit_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t r2w_page_miss_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t r2w_interbank_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t w2r_page_hit_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t w2r_page_miss_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t w2r_interbank_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t w2w_page_hit_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t w2w_page_miss_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t w2w_interbank_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_no_regs_rk_counter rk_counter[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq0_toggle_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq1_toggle_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq2_toggle_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq3_toggle_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq0_toggle_counter_r;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq1_toggle_counter_r;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq2_toggle_counter_r;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq3_toggle_counter_r;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t read_bytes_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t write_bytes_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t max_sref_req_to_ack_latency_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t max_rk1_drs_long_req_to_ack_latency_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t max_rk1_drs_req_to_ack_latency_counter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved10[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lat_counter_cmd[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lat_counter_aver;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lat_counter_num;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lat_counter_block_ale;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved11[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqssamplev;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved12[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsgnwcnt[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t toggle_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs0_err_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq_err_cnt0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs1_err_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq_err_cnt1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs2_err_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq_err_cnt2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs3_err_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq_err_cnt3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved13[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t iorgcnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsg_retry_state;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsg_retry_state1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved14[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t impcal_status1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t impcal_status2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqdrv_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cmddrv_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cmddrv1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cmddrv2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved15[98];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_nao_regs_rk rk[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved25[192];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dvfs_dbg0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dvfs_dbg1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dramc_nao_regs_end;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, testmode, 0x0000);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, lbwdat0, 0x0004);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, lbwdat1, 0x0008);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, lbwdat2, 0x000c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, lbwdat3, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, ckphchk, 0x0020);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dmmonitor, 0x0024);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, testchip_dma1, 0x0030);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, misc_statusa, 0x0080);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, special_status, 0x0084);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, spcmdresp, 0x0088);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, mrr_status, 0x008c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, mrr_status2, 0x0090);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, mrrdata0, 0x0094);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, mrrdata1, 0x0098);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, mrrdata2, 0x009c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, mrrdata3, 0x00a0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, drs_status, 0x00a8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, jmeter_st, 0x00bc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, tcmdo1lat, 0x00c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, rdqc_cmp, 0x00c4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, ckphchk_status, 0x00c8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, hwmrr_push2pop_cnt, 0x010c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, hwmrr_status, 0x0110);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, testrpt, 0x0120);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, cmp_err, 0x0124);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, test_abit_status1, 0x0128);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, test_abit_status2, 0x012c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, test_abit_status3, 0x0130);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, test_abit_status4, 0x0134);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqsdly0, 0x0150);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq_cal_max[0], 0x0154);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqs_cal_min[0], 0x0174);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqs_cal_max[0], 0x0194);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqical0, 0x01b4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqical1, 0x01b8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqical2, 0x01bc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqical3, 0x01c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, testchip_dma_status[0], 0x0200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, refresh_pop_counter, 0x0300);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, freerun_26m_counter, 0x0304);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dramc_idle_counter, 0x0308);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, r2r_page_hit_counter, 0x030c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, r2r_page_miss_counter, 0x0310);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, r2r_interbank_counter, 0x0314);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, r2w_page_hit_counter, 0x0318);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, r2w_page_miss_counter, 0x031c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, r2w_interbank_counter, 0x0320);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, w2r_page_hit_counter, 0x0324);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, w2r_page_miss_counter, 0x0328);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, w2r_interbank_counter, 0x032c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, w2w_page_hit_counter, 0x0330);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, w2w_page_miss_counter, 0x0334);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, w2w_interbank_counter, 0x0338);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq0_toggle_counter, 0x036c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq1_toggle_counter, 0x0370);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq2_toggle_counter, 0x0374);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq3_toggle_counter, 0x0378);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq0_toggle_counter_r, 0x037c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq1_toggle_counter_r, 0x0380);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq2_toggle_counter_r, 0x0384);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq3_toggle_counter_r, 0x0388);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, read_bytes_counter, 0x038c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, write_bytes_counter, 0x0390);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqssamplev, 0x0400);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqsgnwcnt[0], 0x0408);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, toggle_cnt, 0x0420);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqs0_err_cnt, 0x0424);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq_err_cnt0, 0x0428);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqs1_err_cnt, 0x042c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq_err_cnt1, 0x0430);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqs2_err_cnt, 0x0434);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq_err_cnt2, 0x0438);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqs3_err_cnt, 0x043c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dq_err_cnt3, 0x0440);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, iorgcnt, 0x0450);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqsg_retry_state, 0x0454);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqsg_retry_state1, 0x0458);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, impcal_status1, 0x0460);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, impcal_status2, 0x0464);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, dqdrv_status, 0x0468);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, cmddrv_status, 0x046c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, cmddrv1, 0x0470);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_nao_regs, cmddrv2, 0x0474);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_ao_regs_rk {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsosc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_1[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dummy_rd_wdata0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dummy_rd_wdata1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dummy_rd_wdata2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dummy_rd_wdata3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dummy_rd_adr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dummy_rd_bk;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pre_tdqsck[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_2[40];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_ao_regs_shu_rk {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsien;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqscal;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t fine_tune;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsosc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_1[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_odten0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_odten1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_dqsg0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_dqsg1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_dq[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_2[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs2dq_cal1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs2dq_cal2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs2dq_cal3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs2dq_cal4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs2dq_cal5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_3[43];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_ao_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ddrconf0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dramctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misctl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t perfctl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved0[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rstmask;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t padctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ckectrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t drsctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved1[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rkcfg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dramc_pd_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t clkar;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t clkctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selfref_hwsave_flag;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t srefctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t refctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t refctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t refratre_filter;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t zqcs;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrs;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spcmd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t spcmdctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ppr_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpc_option;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t refque_cnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hw_mrr_fun;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrr_bit_mux1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrr_bit_mux2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrr_bit_mux3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mrr_bit_mux4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved2[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test2_5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test2_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test2_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test2_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test2_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test2_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wdt_dbg_signal;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t lbtest;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t catraining1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t catraining2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved4[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t write_lev;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mr_golden;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t slp4_testmode;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsoscr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved5[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dummy_rd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t shuctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t shuctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t shuctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t shuctrl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t shustatus;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved6[70];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t stbcal;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t stbcal1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t stbcal2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t eyescan;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dvfsdll;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved7[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pre_tdqsck[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved8[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t impcal;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t impedamce_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t impedamce_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t impedamce_ctrl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t impedamce_ctrl4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dramc_dbg_sel1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dramc_dbg_sel2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_10[46];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_ao_regs_rk rk[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_16[64];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd0[64];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t actim[7];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t actim_xrt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ac_time_05t;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ac_derating0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ac_derating1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd1[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ac_derating_05t;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd2[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conf[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t stbcal;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsoscthrd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rankctl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ckectrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t odtctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t impcal1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsosc_prd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsoscr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsoscr2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rodtenstb;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pipe;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t test1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_ca1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_ca2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_ca3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_ca4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_ca5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_ca6;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_ca7;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_ca8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_dqs0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t selph_dqs1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t drving[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wodt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t scintv;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqs2dq_tx;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hwset_mr2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hwset_mr13;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t hwset_vrcg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd3[72];</span><br><span style="color: hsl(120, 100%, 40%);">+ union {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_ao_regs_shu_rk rk[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_63[149];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dqsg_retry;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ } shu[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dramc_ao_regs_end;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, ddrconf0, 0x0000);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, dramctrl, 0x0004);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, misctl0, 0x0008);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, perfctl0, 0x000c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, arbctl, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, rstmask, 0x001c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, padctrl, 0x0020);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, ckectrl, 0x0024);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, drsctrl, 0x0028);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, rkcfg, 0x0034);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, dramc_pd_ctrl, 0x0038);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, clkar, 0x003c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, clkctrl, 0x0040);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, selfref_hwsave_flag, 0x0044);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, srefctrl, 0x0048);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, refctrl0, 0x004c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, refctrl1, 0x0050);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, refratre_filter, 0x0054);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, zqcs, 0x0058);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, mrs, 0x005c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, spcmd, 0x0060);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, spcmdctrl, 0x0064);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, ppr_ctrl, 0x0068);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, mpc_option, 0x006c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, refque_cnt, 0x0070);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, hw_mrr_fun, 0x0074);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, mrr_bit_mux1, 0x0078);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, mrr_bit_mux2, 0x007c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, mrr_bit_mux3, 0x0080);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, mrr_bit_mux4, 0x0084);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, test2_5, 0x008c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, test2_0, 0x0090);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, test2_1, 0x0094);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, test2_2, 0x0098);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, test2_3, 0x009c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, test2_4, 0x00a0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, wdt_dbg_signal, 0x00a4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, lbtest, 0x00ac);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, catraining1, 0x00b0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, catraining2, 0x00b4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, write_lev, 0x00bc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, mr_golden, 0x00c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, slp4_testmode, 0x00c4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, dqsoscr, 0x00c8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, dummy_rd, 0x00d0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shuctrl, 0x00d4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shuctrl1, 0x00d8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shuctrl2, 0x00dc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shuctrl3, 0x00e0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shustatus, 0x00e4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, stbcal, 0x0200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, stbcal1, 0x0204);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, stbcal2, 0x0208);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, eyescan, 0x020c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, dvfsdll, 0x0210);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, pre_tdqsck[0], 0x0218);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, pre_tdqsck[1], 0x021c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, pre_tdqsck[2], 0x0220);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, pre_tdqsck[3], 0x0224);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, impcal, 0x022c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, impedamce_ctrl1, 0x0230);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, impedamce_ctrl2, 0x0234);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, impedamce_ctrl3, 0x0238);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, impedamce_ctrl4, 0x023c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, dramc_dbg_sel1, 0x0240);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, dramc_dbg_sel2, 0x0244);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].actim[0], 0x0800);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].actim_xrt, 0x081c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].ac_time_05t, 0x0820);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].ac_derating0, 0x0824);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].ac_derating1, 0x0828);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].ac_derating_05t, 0x0830);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].conf[0], 0x0840);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].rankctl, 0x0858);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].ckectrl, 0x085c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].odtctrl, 0x0860);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].impcal1, 0x0864);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].dqsosc_prd, 0x0868);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].dqsoscr, 0x086c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].dqsoscr2, 0x0870);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].rodtenstb, 0x0874);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].pipe, 0x0878);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].test1, 0x087c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].selph_ca1, 0x0880);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].selph_dqs0, 0x08a0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].selph_dqs1, 0x08a4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].drving[0], 0x08a8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].wodt, 0x08c0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].dqsg, 0x08c4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].scintv, 0x08c8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].misc, 0x08cc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].dqs2dq_tx, 0x08d0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].hwset_mr2, 0x08d4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].hwset_mr13, 0x08d8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].hwset_vrcg, 0x08dc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].rk[0].dqsctl, 0x0A00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[0].dqsg_retry, 0x0c54);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[1].dqsg_retry, 0x1254);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[2].dqsg_retry, 0x1854);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ao_regs, shu[3].dqsg_retry, 0x1e54);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_ddrphy_regs_misc_stberr_rk {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t r;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t f;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_ddrphy_regs_shu_rk {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_20[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ } b[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ca_cmd[10];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_22[14];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_ddrphy_ao_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll6;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll7;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll9;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll10;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll11;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll12;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll13;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll14;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll15;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll16;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved0[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dll_fine_tune[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq[10];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t _rsvd_0[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tx_mck;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t _rsvd_1[11];</span><br><span style="color: hsl(120, 100%, 40%);">+ } b[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ca_dll_fine_tune[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ca_cmd[11];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rfu_0x1c4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rfu_0x1c8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rfu_0x1cc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ca_tx_mck;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved3[11];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_extlb[24];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dvfs_emi_clk;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_vref_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_imp_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_imp_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_shu_opt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_spm_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_spm_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_spm_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_spm_ctrl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_cg_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_cg_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_cg_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_cg_ctrl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_cg_ctrl4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_cg_ctrl5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ctrl0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ctrl1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ctrl2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ctrl3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ctrl4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ctrl5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_extlb_rx[21];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ckmux_sel;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved4[129];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_stberr_rk0_r;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_stberr_rk0_f;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_stberr_rk1_r;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_stberr_rk1_f;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_stberr_rk2_r;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_stberr_rk2_f;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved5[46];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_rxdvs[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rfu_0x5ec;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t b0_rxdvs[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rfu_0x5f8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rfu_0x5fc;</span><br><span style="color: hsl(120, 100%, 40%);">+ union {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rxdvs[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t _rsvd[24];</span><br><span style="color: hsl(120, 100%, 40%);">+ } b[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rxdvs[10];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t _rsvd_b[54];</span><br><span style="color: hsl(120, 100%, 40%);">+ } r[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_2[28];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t b1_rxdvs[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_3[30];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ca_rxdvs0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ca_rxdvs1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_4[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t r0_ca_rxdvs[10];</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dq[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dll[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_16[17];</span><br><span style="color: hsl(120, 100%, 40%);">+ } b[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ca_cmd[13];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ca_dll[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_18[17];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_19[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll20;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t pll21;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_20[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_21[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_ddrphy_regs_shu_rk rk[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ } shu[4];</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, pll1, 0x0000);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, b[0].dll_fine_tune[0], 0x0080);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, b[0].dq[0], 0x0098);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, b[0].tx_mck, 0x00d0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, ca_dll_fine_tune[0], 0x0180);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, ca_cmd[0], 0x0198);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, ca_tx_mck, 0x01d0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_extlb[0], 0x0200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, dvfs_emi_clk, 0x0260);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_vref_ctrl, 0x0264);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_imp_ctrl0, 0x0268);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_imp_ctrl1, 0x026c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_shu_opt, 0x0270);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl0, 0x0274);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl1, 0x0278);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl2, 0x027c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl3, 0x0280);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl0, 0x0284);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl1, 0x0288);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl2, 0x028c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl3, 0x0290);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl4, 0x0294);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl5, 0x0298);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_ctrl0, 0x029c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_ctrl1, 0x02a0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_ctrl2, 0x02a4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_ctrl3, 0x02a8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_ctrl4, 0x02ac);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_ctrl5, 0x02b0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_extlb_rx[0], 0x02b4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, ckmux_sel, 0x0308);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_rxdvs[0], 0x05e0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_rxdvs[1], 0x05e4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, misc_rxdvs[2], 0x05e8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, rfu_0x5ec, 0x05ec);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, b0_rxdvs[0], 0x05f0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, r[0].b[0].rxdvs[0], 0x0600);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, b1_rxdvs[0], 0x0670);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, r[0].b[1].rxdvs[0], 0x0680);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, ca_rxdvs0, 0x06F0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, r0_ca_rxdvs[0], 0x0700);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, r[1].b[1].rxdvs[0], 0x0880);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, r[1].rxdvs[0], 0x0900);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].b[0].dq[0], 0x0c00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].b[1].dq[6], 0x0C98);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].ca_cmd[0], 0x0d00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].ca_dll[0], 0x0d34);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].pll[0], 0x0d80);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].misc0, 0x0DF0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].rk[0].b[0].dq[0], 0x0e00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].rk[0].ca_cmd[9], 0x0ec4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].rk[1].b[0].dq[0], 0x0f00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].rk[1].ca_cmd[9], 0x0fc4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].rk[2].b[0].dq[0], 0x1000);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[0].rk[2].ca_cmd[9], 0x10c4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].b[0].dq[0], 0x1600);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].b[1].dq[0], 0x1680);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].ca_cmd[0], 0x1700);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].ca_dll[0], 0x1734);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].pll[0], 0x1780);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].misc0, 0x17F0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].rk[0].b[0].dq[0], 0x1800);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].rk[0].ca_cmd[0], 0x18A0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].rk[1].b[0].dq[0], 0x1900);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].rk[1].ca_cmd[0], 0x19A0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].rk[2].b[0].dq[0], 0x1A00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[2].rk[2].ca_cmd[0], 0x1AA0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[3].ca_cmd[0], 0x1C00);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[3].pll[0], 0x1C80);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[3].pll20, 0x1CD0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[3].misc0, 0x1CF0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[3].rk[0].ca_cmd[9], 0x1DC4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[3].rk[1].ca_cmd[9], 0x1EC4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_ao_regs, shu[3].rk[2].ca_cmd[9], 0x1FC4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_ddrphy_nao_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_sta_extlb[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved0[29];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_dq_rxdly_trro[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ca_rxdly_trro[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_dqo1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_cao1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ad_rx_dq_o1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_ad_rx_cmd_o1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_phy_rgs_dq;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_phy_rgs_cmd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_phy_stben_b0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_phy_stben_b1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t misc_phy_rgs_stben_cmd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t dramc_ddrphy_nao_regs_end;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_nao_regs, misc_sta_extlb[0], 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_nao_regs, misc_dq_rxdly_trro[0], 0x080);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_nao_regs, misc_dqo1, 0x0180);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_nao_regs, misc_cao1, 0x0184);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_dq, 0x0190);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_cmd, 0x0194);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_nao_regs, misc_phy_stben_b0, 0x0198);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_stben_cmd, 0x01A0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct emi_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cona;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved0[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conb;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved1[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved2[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cond;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cone;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved4[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conf;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved5[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cong;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved6[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conh;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conh_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t coni;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved7[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conj;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved8[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conm;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved9[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t conn;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved10[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t cono;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved11[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mdct;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mdct_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved12[20];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t iocl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t iocl_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t iocm;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t iocm_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved13[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t testb;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved14[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t testc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved15[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t testd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved16[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arba;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved17[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbb;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved18[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved19[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved20[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbe;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved21[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbf;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved22[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved23[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbh;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved24[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbi;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbi_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved25[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbk;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t arbk_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t slct;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved26[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpud_st[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved27[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpus;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved28[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mput;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mput_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t d_st2[32];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved29[96];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmen;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bstp;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bcnt;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved30[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tact;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved31[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tsct;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved32[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wact;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved33[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wsct;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved34[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bact;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved35[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bsct;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved36[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved37[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tsct2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved38[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t tsct3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved39[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wsct2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved40[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wsct3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wsct4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved41[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved42[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved43[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved44[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel6;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved45[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel7;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved46[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved47[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel9;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved48[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t msel10;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved49[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid6;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid7;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid9;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmid10;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved50[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmen1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved51[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmen2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved52[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmrw0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bmrw1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved53[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved54[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved55[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved56[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype5;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved57[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype6;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved58[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype7;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved59[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved60[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype9;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved61[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype10;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved62[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype11;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved63[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype12;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved64[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype13;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved65[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype14;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved66[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype15;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved67[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype16;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved68[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype17;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved69[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype18;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved70[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype19;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved71[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype20;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved72[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ttype21;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved73[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct4;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwst0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwst1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved74[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ex_con;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ex_st0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ex_st1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ex_st2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wp_adr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wp_adr_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wp_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved75[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chker;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chker_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chker_adr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chker_adr_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved76[40];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct0_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved77[43];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ltct0_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ltct1_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ltct2_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ltct3_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved78[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct0_3rd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved79[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct0_4th;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved80[11];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t bwct0_5th;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved81[19];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t slva;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, cona, 0x0000);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, conb, 0x0008);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, conc, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, cond, 0x0018);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, cone, 0x0020);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, conf, 0x0028);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, cong, 0x0030);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, conh, 0x0038);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, conh_2nd, 0x003c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, coni, 0x0040);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, conj, 0x0048);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, conm, 0x0060);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, conn, 0x0068);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, cono, 0x0070);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, mdct, 0x0078);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, mdct_2nd, 0x007c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, iocl, 0x00d0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, iocl_2nd, 0x00d4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, iocm, 0x00d8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, iocm_2nd, 0x00dc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, testb, 0x00e8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, testc, 0x00f0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, testd, 0x00f8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arba, 0x0100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbb, 0x0108);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbc, 0x0110);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbd, 0x0118);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbe, 0x0120);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbf, 0x0128);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbg, 0x0130);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbh, 0x0138);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbi, 0x0140);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, arbi_2nd, 0x0144);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_regs, slct, 0x0158);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chn_emi_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_cona;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_1[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_conb;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_2[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_conc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_3[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_mdct;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_4[11];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_testb;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_5[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_testc;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_6[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_testd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_7[9];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_md_pre_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_8[1];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_md_pre_mask_shf;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_9[45];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_arbi;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_arbi_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_arbj;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_arbj_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_arbk;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_arbk_2nd;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_slct;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_arb_ref;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_10[20];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_rkarb0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_rkarb1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_rkarb2;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_11[144];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_eco3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_12[196];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_emi_shf0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t chn_emi_regs_end;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_cona, 0x0000);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_conb, 0x0008);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_conc, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_mdct, 0x0018);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_testb, 0x0048);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_testc, 0x0050);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_testd, 0x0058);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_md_pre_mask, 0x0080);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_md_pre_mask_shf, 0x0088);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_arbi, 0x0140);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_arbi_2nd, 0x0144);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_arbj, 0x0148);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_arbj_2nd, 0x014c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_arbk, 0x0150);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_arbk_2nd, 0x0154);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_slct, 0x0158);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_arb_ref, 0x015c);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_rkarb0, 0x01b0);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_rkarb1, 0x01b4);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_rkarb2, 0x01b8);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_eco3, 0x03fc);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(chn_emi_regs, chn_emi_shf0, 0x0710);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct emi_mpu_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpu_ctrl;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpu_dbg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_2[62];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpu_sa0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_3[63];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpu_ea0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_4[63];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpu_apc0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_5[319];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mpu_ctrl_d0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rsvd_6[63];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t rg_mask_d0;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_mpu_regs, mpu_dbg, 0x0004);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_mpu_regs, mpu_sa0, 0x0100);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_mpu_regs, mpu_ea0, 0x0200);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_mpu_regs, mpu_apc0, 0x0300);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_mpu_regs, mpu_ctrl_d0, 0x0800);</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(emi_mpu_regs, rg_mask_d0, 0x0900);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STATUSA_REFRESH_QUEUE_CNT_MASK = 0x0f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMDRESP_RDDQC_RESPONSE_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMDRESP_ZQLAT_RESPONSE_SHIFT = 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMDRESP_ZQC_RESPONSE_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TESTRPT_DM_CMP_CPT_RK0_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DDRCONF0_DM4TO1MODE_SHIFT = 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ DDRCONF0_RDATRST_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DRAMCTRL_ADRDECEN_TARKMODE_SHIFT = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ PERFCTL0_RWOFOEN_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RSTMASK_RSV_DRAM_SUPPORT_RANK_NUM_SHIFT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ PADCTRL_DQIENLATEBEGIN_SHIFT = 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ PADCTRL_DQIENQKEND_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PADCTRL_DQIENQKEND_MASK = 0x00000003,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ RKCFG_RKSWAP_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ RKCFG_RKMODE_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ RKCFG_RKMODE_MASK = 0x00000070,</span><br><span style="color: hsl(120, 100%, 40%);">+ RKCFG_TXRANKFIX_SHIFT = 3,</span><br><span style="color: hsl(120, 100%, 40%);">+ RKCFG_TXRANK_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ RKCFG_TXRANK_MASK = 0x00000003,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ REFCTRL0_REFDIS_SHIFT = 29,</span><br><span style="color: hsl(120, 100%, 40%);">+ REFCTRL0_PBREFEN_SHIFT = 18,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MPCRK_SHIFT = 28,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MPCRK_MASK = 0x30000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSRK_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSRK_MASK = 0x03000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSMA_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSMA_MASK = 0x001fff00,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSOP_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ MRS_MRSOP_MASK = 0x000000ff,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMD_DQSGCNTRST_SHIFT = 9,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMD_DQSGCNTEN_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMD_RDDQCEN_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMD_ZQLATEN_SHIFT = 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMD_ZQCEN_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMD_MRWEN_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SPCMDCTRL_RDDQCDIS_SHIFT = 11,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MPC_OPTION_MPCRKEN_SHIFT = 17,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_0_PAT0_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_0_PAT0_MASK = 0x0000ff00,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_0_PAT1_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_0_PAT1_MASK = 0x000000ff,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TEST2W_SHIFT = 31,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TEST2R_SHIFT = 30,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TEST1_SHIFT = 29,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TESTAUDPAT_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TESTCNT_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_3_TESTCNT_MASK = 0x0000000f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAGENTRKSEL_MASK = 0x70000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAGENTRK_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAGENTRK_MASK = 0x03000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TEST_REQ_LEN1_SHIFT = 17,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTXTALKPAT_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDMODE_SHIFT = 15,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDBITINV_SHIFT = 14,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINIT_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINIT_MASK = 0x00001f00,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTSSOXTALKPAT_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTSSOPAT_SHIFT = 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINC_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ TEST2_4_TESTAUDINC_MASK = 0x0000001f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MR_GOLDEN_MR15_GOLDEN_MASK = 0x0000ff00,</span><br><span style="color: hsl(120, 100%, 40%);">+ MR_GOLDEN_MR20_GOLDEN_MASK = 0x000000ff,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DQSOSCR_AR_COARSE_TUNE_DQ_SW_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ DUMMY_RD_DQSG_DMYWR_EN_SHIFT = 23,</span><br><span style="color: hsl(120, 100%, 40%);">+ DUMMY_RD_DQSG_DMYRD_EN_SHIFT = 22,</span><br><span style="color: hsl(120, 100%, 40%);">+ DUMMY_RD_SREF_DMYRD_EN_SHIFT = 21,</span><br><span style="color: hsl(120, 100%, 40%);">+ DUMMY_RD_DUMMY_RD_EN_SHIFT = 20,</span><br><span style="color: hsl(120, 100%, 40%);">+ DUMMY_RD_DMY_RD_DBG_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ DUMMY_RD_DMY_WR_DBG_SHIFT = 6,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHUCTRL2_R_DVFS_OPTION_SHIFT = 15,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHUCTRL2_R_DVFS_PARK_N_SHIFT = 14,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ STBCAL_DQSIENMODE_SELPH_SHIFT = 30,</span><br><span style="color: hsl(120, 100%, 40%);">+ STBCAL_STBCALEN_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ STBCAL_STB_SELPHYCALEN_SHIFT = 22,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ STBCAL1_STBCNT_LATCH_EN_SHIFT = 11,</span><br><span style="color: hsl(120, 100%, 40%);">+ STBCAL1_STBENCMPEN_SHIFT = 10,</span><br><span style="color: hsl(120, 100%, 40%);">+ STBCAL1_DQSIEN_7_COARSE_TUNE_EN_SHIFT = 5,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_ACTIM_XRT_XRTR2R_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_ACTIM_XRT_XRTR2R_MASK = 0x0000000f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_CONF1_DATLAT_DSEL_PHY_SHIFT = 26,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_CONF1_DATLAT_DSEL_PHY_MASK = 0x7c000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_CONF1_DATLAT_DSEL_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_CONF1_DATLAT_DSEL_MASK = 0x00001f00,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_CONF1_DATLAT_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_CONF1_DATLAT_MASK = 0x0000001f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_PHY_SHIFT = 28,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_PHY_MASK = 0xf0000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_ROOT1_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_ROOT1_MASK = 0x0f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_SHIFT = 20,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_RANKCTL_RANKINCTL_MASK = 0x00f00000,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_ODTCTRL_RODT_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU_ODTCTRL_RODT_MASK = 0x000000f0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_WODT_DBIWR_SHIFT = 29,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_DQSCTL_DQSINCTL_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_DQSCTL_DQSINCTL_MASK = 0x0000000f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_MASK = 0x00000070,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_MASK = 0x00000007,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0_SHIFT = 14,</span><br><span style="color: hsl(120, 100%, 40%);">+ B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0_MASK = 0x0000c000,</span><br><span style="color: hsl(120, 100%, 40%);">+ B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0_SHIFT = 5,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1_SHIFT = 14,</span><br><span style="color: hsl(120, 100%, 40%);">+ B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1_MASK = 0x0000c000,</span><br><span style="color: hsl(120, 100%, 40%);">+ B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1_SHIFT = 5,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT = 25,</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_CTRL1_R_DMAR_FINE_TUNE_DQ_SW_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_CTRL1_R_DMPHYRST_SHIFT = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STBERR_RK_R_STBERR_RK_R_MASK = 0x0000ffff,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MISC_STBERR_RK_F_STBERR_RK_F_MASK = 0x0000ffff,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK = 0x0000003f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_R_DMRANKRXDVS_B0_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_R_DMRANKRXDVS_B0_MASK = 0x0000000f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1_MASK = 0x0000003f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_R_DMDQMDBI_SHU_B1_SHIFT = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_R_DMRANKRXDVS_B1_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_R_DMRANKRXDVS_B1_MASK = 0x0000000f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_SHIFT = 12,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK = 0x00007000,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT = 10,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK = 0x00000c00,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ6_RK_RX_ARDQS0_F_DLY_B0_MASK = 0x7f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ6_RK_RX_ARDQS0_R_DLY_B0_MASK = 0x007f0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ6_RK_RX_ARDQM0_F_DLY_B0_MASK = 0x00003f00,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ6_RK_RX_ARDQM0_R_DLY_B0_MASK = 0x0000003f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_PBYTE_B0_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_PBYTE_B0_MASK = 0x3f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQM_B0_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQM_B0_MASK = 0x003f0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQ_B0_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B0_DQ7_RK_ARFINE_TUNE_DQ_B0_MASK = 0x00003f00,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_PBYTE_B1_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_PBYTE_B1_MASK = 0x3f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQM_B1_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQM_B1_MASK = 0x003f0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQ_B1_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_B1_DQ7_RK_ARFINE_TUNE_DQ_B1_MASK = 0x00003f00,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK = 0x3f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK = 0x0000003f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1_MASK = 0x0f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1_SHIFT = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1_MASK = 0x0000000f,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ7_RK2_ARFINE_TUNE_PBYTE_B1_SHIFT = 24,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ7_RK2_ARFINE_TUNE_PBYTE_B1_MASK = 0x3f000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ7_RK2_ARFINE_TUNE_DQM_B1_SHIFT = 16,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ7_RK2_ARFINE_TUNE_DQM_B1_MASK = 0x003f0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ7_RK2_ARFINE_TUNE_DQ_B1_SHIFT = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ SHU1_R2_B1_DQ7_RK2_ARFINE_TUNE_DQ_B1_MASK = 0x00003f00,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct dramc_channel_regs {</span><br><span style="color: hsl(120, 100%, 40%);">+ union {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_ddrphy_ao_regs phy;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t size_ddrphy_ao_regs[0x2000];</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ union {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_ao_regs ao;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t size_ao_regs[0x2000];</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ union {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_nao_regs nao;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t size_nao_regs[0x1000];</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ union {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct chn_emi_regs emi;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t size_emi_regs[0x1000];</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ union {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dramc_ddrphy_nao_regs phy_nao;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t size_ddrphy_nao_regs[0x2000];</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct dramc_channel_regs *const ch = (void *)DRAMC_CH_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+static struct emi_mpu_regs *const emi_mpu = (void *)EMI_MPU_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _DRAMC_REGISTER_H_ */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>index edc27a8..5969450 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/emi.h</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017 MediaTek Inc.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -18,7 +18,26 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_common_mt8183.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct sdram_params {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 impedance[2][4];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 wr_level[CHANNEL_NUM][RANK_MAX][DQS_NUMBER];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 cbt_cs[CHANNEL_NUM][RANK_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 cbt_mr12[CHANNEL_NUM][RANK_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 clk_delay;</span><br><span style="color: hsl(120, 100%, 40%);">+ s8 dqs_delay[CHANNEL_NUM];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 EMI_CONA_VAL;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 EMI_CONH_VAL;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 EMI_CONF_VAL;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 CHN_EMI_CONA_VAL[CHANNEL_NUM];</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cbt_mode_extern;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int complex_mem_test(u8 *start, unsigned int len);</span><br><span> size_t sdram_size(void);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct sdram_params *get_sdram_config(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_set_emi(const struct sdram_params *params);</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_mem_init(const struct sdram_params *params);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_MEDIATEK_MT8183_EMI_H */</span><br><span>diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld</span><br><span>index f148eed..2a6d42d 100644</span><br><span>--- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld</span><br><span>@@ -39,7 +39,7 @@</span><br><span> SRAM_END(0x00120000)</span><br><span> </span><br><span> SRAM_L2C_START(0x00200000)</span><br><span style="color: hsl(0, 100%, 40%);">- OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 92K)</span><br><span style="color: hsl(120, 100%, 40%);">+ OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 110K)</span><br><span> BOOTBLOCK(0x00227000, 89K)</span><br><span> VERSTAGE(0x0023E000, 114K)</span><br><span> SRAM_L2C_END(0x00280000)</span><br><span>diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c</span><br><span>new file mode 100644</span><br><span>index 0000000..7fee8b8</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/mediatek/mt8183/memory.c</span><br><span>@@ -0,0 +1,51 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 MediaTek Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/dramc_pi_api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/emi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <symbols.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mt_mem_init(const struct sdram_params *params)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 rank_size[RANK_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* memory calibration */</span><br><span style="color: hsl(120, 100%, 40%);">+ mt_set_emi(params);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_MEMORY_TEST)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t r;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *addr = _dram;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_dram_rank_size(&rank_size[0]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (r = RANK_0; r < RANK_MAX; r++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (rank_size[r] == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ i = complex_mem_test(addr, 0x2000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s : %d\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ (i == 0) ? "pass" : "fail", i);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ASSERT(i == 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ addr += rank_size[r];</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c</span><br><span>index e0dd388..b099e99 100644</span><br><span>--- a/src/soc/mediatek/mt8183/pll.c</span><br><span>+++ b/src/soc/mediatek/mt8183/pll.c</span><br><span>@@ -280,6 +280,35 @@</span><br><span> setbits_le32(pll->div_reg, PLL_PCW_CHG);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void mem_pll_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int tmp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLKSQ Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_apmixed->ap_pll_con0, 0x85);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CLKSQ LPF Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_apmixed->ap_pll_con0, 0x87);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* power on MPLL */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_apmixed->mpll_pwr_con0, 0x3);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* turn off ISO of MPLL */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_apmixed->mpll_pwr_con0, 0x1);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = read32(&mtk_apmixed->mpll_con1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Config MPLL freq */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_apmixed->mpll_con1, tmp | 0x80000000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enable MPLL */</span><br><span style="color: hsl(120, 100%, 40%);">+ setbits_le32(&mtk_apmixed->mpll_con0, 0x181);</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(20);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void mt_pll_init(void)</span><br><span> {</span><br><span> int i;</span><br><span>@@ -348,4 +377,6 @@</span><br><span> </span><br><span> /* enable [14] dramc_pll104m_ck */</span><br><span> setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_pll_init();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28437">change 28437</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28437"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaaa1db170c168a58b020095ae45d98355d8dfcb0 </div>
<div style="display:none"> Gerrit-Change-Number: 28437 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>