<p>Xiang Wang <strong>uploaded patch set #3</strong> to this change.</p><p><a href="https://review.coreboot.org/28384">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: add entry assembly file for RAMSTAGE<br><br>RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling<br>needs to be moved to ddr memory. So add a assembly file to do this.<br><br>Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/Makefile.inc<br>A src/arch/riscv/assembly_entry.S<br>M src/arch/riscv/include/arch/header.ld<br>3 files changed, 59 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28384/3</pre><p>To view, visit <a href="https://review.coreboot.org/28384">change 28384</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28384"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d </div>
<div style="display:none"> Gerrit-Change-Number: 28384 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>
<div style="display:none"> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>
<div style="display:none"> Gerrit-Reviewer: Shawn Chang <citypw@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>