<p><a href="https://review.coreboot.org/20472">View Change</a></p><p>10 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c">File src/northbridge/intel/sandybridge/pcie.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@52">Patch Set #7, Line 52:</a> <code style="font-family:monospace,monospace">static void pcie_programm_da0(device_t dev, u8 val)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'programm' may be misspelled - perhaps 'program'?</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@97">Patch Set #7, Line 97:</a> <code style="font-family:monospace,monospace">static void pcie_programm_90x(device_t dev, u8 bundle, u8 a, u8 b)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'programm' may be misspelled - perhaps 'program'?</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@128">Patch Set #7, Line 128:</a> <code style="font-family:monospace,monospace">             /* Programm test values */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'Programm' may be misspelled - perhaps 'Program'?</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@129">Patch Set #7, Line 129:</a> <code style="font-family:monospace,monospace">              pcie_programm_90x(dev, bundle, a[i], i);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'programm' may be misspelled - perhaps 'program'?</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@138">Patch Set #7, Line 138:</a> <code style="font-family:monospace,monospace">                /* No errors occured after 100msec ? */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'occured' may be misspelled - perhaps 'occurred'?</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@177">Patch Set #7, Line 177:</a> <code style="font-family:monospace,monospace"> for (bundle = 0; bundle < end_bundle; bundle ++) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space prohibited before that '++' (ctx:WxB)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@190">Patch Set #7, Line 190:</a> <code style="font-family:monospace,monospace">                 /* Programm 0xda0 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'Programm' may be misspelled - perhaps 'Program'?</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@191">Patch Set #7, Line 191:</a> <code style="font-family:monospace,monospace">                    pcie_programm_da0(dev, reg_da0[i]);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'programm' may be misspelled - perhaps 'program'?</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@226">Patch Set #7, Line 226:</a> <code style="font-family:monospace,monospace">             /* Programm 0xda0 */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'Programm' may be misspelled - perhaps 'Program'?</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/20472/7/src/northbridge/intel/sandybridge/pcie.c@227">Patch Set #7, Line 227:</a> <code style="font-family:monospace,monospace">            pcie_programm_da0(dev, reg_da0[best_da0]);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'programm' may be misspelled - perhaps 'program'?</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/20472">change 20472</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20472"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
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<div style="display:none"> Gerrit-Change-Id: I80a106b1f969103206f24dc5c4b268503acfa81f </div>
<div style="display:none"> Gerrit-Change-Number: 20472 </div>
<div style="display:none"> Gerrit-PatchSet: 7 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Dan Elkouby <streetwalkermc@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Iru Cai <mytbk920423@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Thu, 30 Aug 2018 14:44:34 +0000 </div>
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