<p>Xiang Wang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28384">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: add entry assembly file for RAMSTAGE<br><br>RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling<br>needs to be moved to ddr memory. So add a assembly file to do this.<br><br>Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/Makefile.inc<br>A src/arch/riscv/assembly_entry.S<br>M src/arch/riscv/include/arch/header.ld<br>3 files changed, 58 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28384/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc</span><br><span>index c485940..4038964 100644</span><br><span>--- a/src/arch/riscv/Makefile.inc</span><br><span>+++ b/src/arch/riscv/Makefile.inc</span><br><span>@@ -97,6 +97,10 @@</span><br><span> ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)</span><br><span> </span><br><span> ramstage-y =</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += assembly_entry.S</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += mcall.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += trap_util.S</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += trap_handler.c</span><br><span> ramstage-y += virtual_memory.c</span><br><span> ramstage-y += stages.c</span><br><span> ramstage-y += misc.c</span><br><span>diff --git a/src/arch/riscv/assembly_entry.S b/src/arch/riscv/assembly_entry.S</span><br><span>new file mode 100644</span><br><span>index 0000000..724de92</span><br><span>--- /dev/null</span><br><span>+++ b/src/arch/riscv/assembly_entry.S</span><br><span>@@ -0,0 +1,52 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/encoding.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <mcall.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.section ".text._start", "ax", %progbits</span><br><span style="color: hsl(120, 100%, 40%);">+.globl _start</span><br><span style="color: hsl(120, 100%, 40%);">+_start:</span><br><span style="color: hsl(120, 100%, 40%);">+ # initialize stack point for each hart</span><br><span style="color: hsl(120, 100%, 40%);">+ # and the stack must be page-aligned.</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0xDEADBEEF used to check stack overflow</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr a0, mhartid</span><br><span style="color: hsl(120, 100%, 40%);">+ la t0, _stack</span><br><span style="color: hsl(120, 100%, 40%);">+ slli t1, a0, RISCV_PGSHIFT</span><br><span style="color: hsl(120, 100%, 40%);">+ add t0, t0, t1</span><br><span style="color: hsl(120, 100%, 40%);">+ li t1, 0xDEADBEEF</span><br><span style="color: hsl(120, 100%, 40%);">+ sd t1, 0(t0)</span><br><span style="color: hsl(120, 100%, 40%);">+ li t1, RISCV_PGSIZE - HLS_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ add sp, t0, t1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # initialize hart-local storage</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr a0, mhartid</span><br><span style="color: hsl(120, 100%, 40%);">+ call hls_init</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # initialize entry of interrupt/exception</span><br><span style="color: hsl(120, 100%, 40%);">+ la t0, trap_entry</span><br><span style="color: hsl(120, 100%, 40%);">+ csrw mtvec, t0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # clear any pending interrupts</span><br><span style="color: hsl(120, 100%, 40%);">+ csrwi mip, 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ call exit_car</span><br><span style="color: hsl(120, 100%, 40%);">+ # set up the mstatus register for VM</span><br><span style="color: hsl(120, 100%, 40%);">+ call mstatus_init</span><br><span style="color: hsl(120, 100%, 40%);">+ tail main</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # These codes need to be implemented on a specific SoC</span><br><span style="color: hsl(120, 100%, 40%);">+ .weak exit_car</span><br><span style="color: hsl(120, 100%, 40%);">+exit_car:</span><br><span style="color: hsl(120, 100%, 40%);">+ ret</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld</span><br><span>index 3e078d8..2edcd67 100644</span><br><span>--- a/src/arch/riscv/include/arch/header.ld</span><br><span>+++ b/src/arch/riscv/include/arch/header.ld</span><br><span>@@ -23,6 +23,8 @@</span><br><span> </span><br><span> #ifdef __BOOTBLOCK__</span><br><span> ENTRY(_start)</span><br><span style="color: hsl(120, 100%, 40%);">+#elif __RAMSTAGE__</span><br><span style="color: hsl(120, 100%, 40%);">+ENTRY(_start)</span><br><span> #else</span><br><span> ENTRY(stage_entry)</span><br><span> #endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28384">change 28384</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28384"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d </div>
<div style="display:none"> Gerrit-Change-Number: 28384 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>