<p>Xiang Wang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28383">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: separately define stack locations at different stages<br><br>BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begin<br>execution will enable cache, then CAR will disappear. So the<br>Stack will be separated.<br><br>Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/include/arch/memlayout.h<br>M src/soc/sifive/fu540/include/soc/memlayout.ld<br>2 files changed, 15 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28383/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h</span><br><span>index 9097cf5..bbd0231 100644</span><br><span>--- a/src/arch/riscv/include/arch/memlayout.h</span><br><span>+++ b/src/arch/riscv/include/arch/memlayout.h</span><br><span>@@ -20,6 +20,18 @@</span><br><span> </span><br><span> #define STACK(addr, size) REGION(stack, addr, size, 4096)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_BOOTBLOCK || ENV_ROMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+# define CAR_STACK(addr, size) REGION(stack, addr, size, 4096)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+# define CAR_STACK(addr, size)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_RAMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+# define MEM_STACK(addr, size) REGION(stack, addr, size, 4096)</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+# define MEM_STACK(addr, size)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* TODO: Need to add DMA_COHERENT region like on ARM? */</span><br><span> </span><br><span> #endif /* __ARCH_MEMLAYOUT_H */</span><br><span>diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld</span><br><span>index a03c03d..b9b9c47 100644</span><br><span>--- a/src/soc/sifive/fu540/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/sifive/fu540/include/soc/memlayout.ld</span><br><span>@@ -25,11 +25,12 @@</span><br><span> {</span><br><span>      L2LIM_START(FU540_L2LIM)</span><br><span>     BOOTBLOCK(FU540_L2LIM, 64K)</span><br><span style="color: hsl(0, 100%, 40%);">-     STACK(FU540_L2LIM + 64K, 4K)</span><br><span style="color: hsl(0, 100%, 40%);">-    PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K)</span><br><span style="color: hsl(120, 100%, 40%);">+   CAR_STACK(FU540_L2LIM + 64K, 20K)</span><br><span style="color: hsl(120, 100%, 40%);">+     PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)</span><br><span>  ROMSTAGE(FU540_L2LIM + 128K, 128K)</span><br><span>   L2LIM_END(FU540_L2LIM + 2M)</span><br><span> </span><br><span>      DRAM_START(FU540_DRAM)</span><br><span>       RAMSTAGE(FU540_DRAM, 256K)</span><br><span style="color: hsl(120, 100%, 40%);">+    MEM_STACK(FU540_DRAM + 256K, 20K)</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28383">change 28383</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28383"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 </div>
<div style="display:none"> Gerrit-Change-Number: 28383 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>