<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28369">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.h<br><br>Google is creating code to measure AGESA performance, which needs structure<br>TP_Perf_STRUCT and associated definitions. In preparation to remove IDS<br>headers, move the necessary definitions to AGESA.h.<br><br>BUG=b:112885948<br>TEST=Build grunt<br><br>Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/vendorcode/amd/pi/00670F00/AGESA.h<br>M src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h<br>M src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h<br>3 files changed, 119 insertions(+), 119 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28369/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h</span><br><span>index 2eee41b..fbe93bd 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/AGESA.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/AGESA.h</span><br><span>@@ -3581,6 +3581,125 @@</span><br><span> </span><br><span> #ifndef IDS_CALLOUT_INIT</span><br><span> #define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IDS_PERF_VERSION 0x00010001ul //version number 0.1.0.1</span><br><span style="color: hsl(120, 100%, 40%);">+/// Time points performance function used</span><br><span style="color: hsl(120, 100%, 40%);">+/// N O T E: NEVER change below defination, any new TP MUST be appended to the end of this enum</span><br><span style="color: hsl(120, 100%, 40%);">+ typedef enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGININITENV = 0x10C, ///< BeginInitEnv</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDINITENV = 0x10D, ///< EndInitEnv</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGININITMID = 0x11E, ///< BeginInitMid</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDINITMID = 0x11F, ///< EndInitMid</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGININITRESET = 0x12E, ///< BeginInitReset</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDINITRESET = 0x12F, ///< EndInitReset</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBINITATRTB = 0x154, ///< BeginGnbInitAtRtb</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBINITATRTB = 0x155, ///< EndGnbInitAtRtb</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINDISPATCHCPUFEATURESINITRTB = 0x15A, ///< BeginDispatchCpuFeaturesInitRtb</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDDISPATCHCPUFEATURESINITRTB = 0x15B, ///< EndDispatchCpuFeaturesInitRtb</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAMDCPUMID = 0x15C, ///< BeginAmdCpuEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAMDCPUMID = 0x15D, ///< EndAmdCpuEarly</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_BEGINAMDGNBMIDLATE = 0x15E, ///< BeginAmdGnbMidLate</span><br><span style="color: hsl(120, 100%, 40%);">+ TP_ENDAMDAMDGNBMIDLATE = 0x15F, ///< EndAmdGnbMidLate</span><br><span style="color: hsl(120, 100%, 40%);">+ IDS_TP_END ///< End of IDS TP list</span><br><span style="color: hsl(120, 100%, 40%);">+ } IDS_PERF_DATA;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/// Data Structure of Parameters for TestPoint_TSC.</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 LineInFile; ///< Line of current time counter</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 Description; ///<Description ID</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC</span><br><span style="color: hsl(120, 100%, 40%);">+} TestPoint_TSC;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define RESERVED_TP_NUMER 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY + 1 + RESERVED_TP_NUMER)</span><br><span style="color: hsl(120, 100%, 40%);">+/// Data Structure of Parameters for TP_Perf_STRUCT.</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Signature; ///< "PERF"</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Version; ///< version</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Index; ///< The Index of TP_Perf_STRUCT</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TscInMhz; ///< Tsc counter in 1 mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT</span><br><span style="color: hsl(120, 100%, 40%);">+} TP_Perf_STRUCT;</span><br><span> #endif</span><br><span> </span><br><span> /************************************************************************</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h</span><br><span>index 40feef6..edb48ac 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h</span><br><span>@@ -43,106 +43,5 @@</span><br><span> #include <check_for_wrapper.h></span><br><span> </span><br><span> #ifndef _IDS_PERFORMANCE_DATA_POINT</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define _IDS_PERFORMANCE_DATA_POINT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_PERF_VERSION 0x00010001ul //version number 0.1.0.1</span><br><span style="color: hsl(0, 100%, 40%);">-/// Time points performance function used</span><br><span style="color: hsl(0, 100%, 40%);">-/// N O T E: NEVER change below defination, any new TP MUST be appended to the end of this enum</span><br><span style="color: hsl(0, 100%, 40%);">- typedef enum {</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGININITENV = 0x10C, ///< BeginInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDINITENV = 0x10D, ///< EndInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGININITMID = 0x11E, ///< BeginInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDINITMID = 0x11F, ///< EndInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGININITRESET = 0x12E, ///< BeginInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDINITRESET = 0x12F, ///< EndInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATRTB = 0x154, ///< BeginGnbInitAtRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATRTB = 0x155, ///< EndGnbInitAtRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINDISPATCHCPUFEATURESINITRTB = 0x15A, ///< BeginDispatchCpuFeaturesInitRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDDISPATCHCPUFEATURESINITRTB = 0x15B, ///< EndDispatchCpuFeaturesInitRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDCPUMID = 0x15C, ///< BeginAmdCpuEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDCPUMID = 0x15D, ///< EndAmdCpuEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDGNBMIDLATE = 0x15E, ///< BeginAmdGnbMidLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDAMDGNBMIDLATE = 0x15F, ///< EndAmdGnbMidLate</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_TP_END ///< End of IDS TP list</span><br><span style="color: hsl(0, 100%, 40%);">- } IDS_PERF_DATA;</span><br><span> #endif</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h b/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h</span><br><span>index d53878f..167ac6f 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h</span><br><span>@@ -45,22 +45,4 @@</span><br><span> #ifndef _IDS_LIB_H_</span><br><span> #define _IDS_LIB_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/// Data Structure of Parameters for TestPoint_TSC.</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 LineInFile; ///< Line of current time counter</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 Description; ///<Description ID</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC</span><br><span style="color: hsl(0, 100%, 40%);">-} TestPoint_TSC;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RESERVED_TP_NUMER 0x20</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY + 1 + RESERVED_TP_NUMER)</span><br><span style="color: hsl(0, 100%, 40%);">-/// Data Structure of Parameters for TP_Perf_STRUCT.</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Signature; ///< "PERF"</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Version; ///< version</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Index; ///< The Index of TP_Perf_STRUCT</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 TscInMhz; ///< Tsc counter in 1 mhz</span><br><span style="color: hsl(0, 100%, 40%);">- TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT</span><br><span style="color: hsl(0, 100%, 40%);">-} TP_Perf_STRUCT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #endif //_IDS_LIB_H_</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28369">change 28369</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28369"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134 </div>
<div style="display:none"> Gerrit-Change-Number: 28369 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>