<p>Tom Hiller has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28354">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation: fix sphinx warnings<br><br>Fix warning from list in table cells for nri_registers.md<br><br>Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c<br>Signed-off-by: Tom Hiller <thrilleratplay@gmail.com><br>---<br>M Documentation/northbridge/intel/sandybridge/nri_registers.md<br>1 file changed, 42 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28354/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md</span><br><span>index d5857ec..e47522e 100644</span><br><span>--- a/Documentation/northbridge/intel/sandybridge/nri_registers.md</span><br><span>+++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md</span><br><span>@@ -1522,13 +1522,20 @@</span><br><span> | 24:27| tWR |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 29 | Command 3-state options |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0: Drive when channel is active, tri-state when inactive, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 1: Always drive command bus |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 30:31| CMD stretch, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 00b: 1N, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 10b: 2N, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 11b: 3N |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> ```</span><br><span> </span><br><span>@@ -1896,14 +1903,23 @@</span><br><span> | | plus burst length. |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 8:10| PDWN_mode, selects the mode of power-down: |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0x0: No power down, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0x1: APD, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0x2: PPD, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0x3: APD+PPD, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0x4: Reserved, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0x5: Reserved, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0x6: PPD-DLLoff, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0x7: APD+PPD+DLLof |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> ```</span><br><span> </span><br><span>@@ -1973,19 +1989,31 @@</span><br><span> | Bit | Description |</span><br><span> +===========+==================================================================+</span><br><span> | 0:1| CH_A, defines the largest channel. |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 00b: Channel 0, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 01b: Channel 1, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 10b: Channel 2 |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 2:3| CH_B, defines the mid-size channel. |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 00b: Channel 0, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 01b: Channel 1, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 10b: Channel 2 |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 2:3| CH_C, defines the smallest channel. |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 00b: Channel 0, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 01b: Channel 1, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 10b: Channel 2, CH_C is 10 if only 2 channels are supported |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> ```</span><br><span> </span><br><span>@@ -2002,8 +2030,11 @@</span><br><span> | 0:7| DIMMA size in 256 MB multiples |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 16 | DIMM A select (DAS) Slot to DIMM mapping, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0: DIMMA, DIMMB, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 1: DIMMB, DIMMA |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 17 | DIMM A number of ranks |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span>@@ -2025,9 +2056,13 @@</span><br><span> | | 20-27 to use for high rank interleave |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 24:25| ECC, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 00b: No ECC active, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 01b: ECC is active on IO, |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 11b: ECC is active on both IO and ECC logic |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> ```</span><br><span> </span><br><span>@@ -2121,7 +2156,9 @@</span><br><span> | Bit | Description |</span><br><span> +===========+==================================================================+</span><br><span> | 0:31| Inject error when ECC_inj_Addr_Compare[31:0] = |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | ADDR[37:6] && ECC_Inj_Addr_Mask[31:0] |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> ```</span><br><span> </span><br><span>@@ -2138,7 +2175,9 @@</span><br><span> | 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 8 | - 1: 100Mhz reference clock |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 0: 133Mhz reference clock (Ivy Bridge only) |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 31 | PLL busy |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span>@@ -2155,8 +2194,11 @@</span><br><span> | Bit | Description |</span><br><span> +===========+==================================================================+</span><br><span> | 0:7| Active multiplier: |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 100Mhz [7,12], |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> | | - 133Mhz [3,19] |</span><br><span style="color: hsl(120, 100%, 40%);">+| | |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> ```</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28354">change 28354</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c </div>
<div style="display:none"> Gerrit-Change-Number: 28354 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tom Hiller <thrilleratplay@gmail.com> </div>