<p>Philipp Deppenwiese <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/28022">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cn81xx: Add vboot support<br><br>* Add VERSTAGE and VBOOT_WORK to memlayout.<br>* Add hard and soft reset.<br>* Add missing makefile and kconfig includes.<br><br>Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad<br>Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org><br>Reviewed-on: https://review.coreboot.org/28022<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/soc/cavium/cn81xx/Kconfig<br>M src/soc/cavium/cn81xx/Makefile.inc<br>M src/soc/cavium/cn81xx/include/soc/addressmap.h<br>M src/soc/cavium/cn81xx/include/soc/memlayout.ld<br>A src/soc/cavium/cn81xx/reset.c<br>5 files changed, 49 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig</span><br><span>index edc9480..24d386c 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Kconfig</span><br><span>+++ b/src/soc/cavium/cn81xx/Kconfig</span><br><span>@@ -17,6 +17,11 @@</span><br><span> </span><br><span> if SOC_CAVIUM_CN81XX</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_SEPARATE_VERSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_RETURN_FROM_VERSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config ARM64_BL31_EXTERNAL_FILE</span><br><span> string</span><br><span> default "3rdparty/blobs/soc/cavium/cn81xx/bl31.elf"</span><br><span>diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>index 2179bc7..d212715 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>+++ b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>@@ -25,11 +25,24 @@</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += uart.c</span><br><span> bootblock-y += cpu.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += reset.c</span><br><span> ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)</span><br><span> bootblock-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> endif</span><br><span> </span><br><span> ################################################################################</span><br><span style="color: hsl(120, 100%, 40%);">+# verstage</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += twsi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += clock.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += timer.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += cbmem.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += reset.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+################################################################################</span><br><span> # romstage</span><br><span> </span><br><span> romstage-y += twsi.c</span><br><span>@@ -40,6 +53,7 @@</span><br><span> romstage-y += uart.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> romstage-y += cbmem.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += reset.c</span><br><span> </span><br><span> romstage-y += sdram.c</span><br><span> romstage-y += mmu.c</span><br><span>@@ -60,6 +74,7 @@</span><br><span> ramstage-y += cpu_secondary.S</span><br><span> ramstage-y += ecam0.c</span><br><span> ramstage-y += cbmem.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += reset.c</span><br><span> </span><br><span> ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c</span><br><span> </span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h</span><br><span>index f698306..f188961 100644</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/addressmap.h</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h</span><br><span>@@ -62,6 +62,7 @@</span><br><span> </span><br><span> /* RST */</span><br><span> #define RST_PF_BAR0 (0x87E006000000ULL + 0x1600)</span><br><span style="color: hsl(120, 100%, 40%);">+#define RST_SOFT_RESET (RST_PF_BAR0 + 0x80ULL)</span><br><span> #define RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL)</span><br><span> #define RST_PP_RESET (RST_PF_BAR0 + 0x140ULL)</span><br><span> #define RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL)</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>index b80d152..e3bf61f 100644</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>@@ -28,14 +28,18 @@</span><br><span> /* Insecure region 1MiB - TOP OF DRAM */</span><br><span> /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */</span><br><span> SRAM_START(BOOTROM_OFFSET)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> STACK(BOOTROM_OFFSET, 16K)</span><br><span> TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K)</span><br><span> PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K)</span><br><span> PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)</span><br><span style="color: hsl(120, 100%, 40%);">+ VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)</span><br><span style="color: hsl(120, 100%, 40%);">+ VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K)</span><br><span> ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> SRAM_END(BOOTROM_OFFSET + 0x80000)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> TTB(BOOTROM_OFFSET + 0x80000, 512K)</span><br><span> RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K)</span><br><span> /* Stack for secondary CPUs */</span><br><span>diff --git a/src/soc/cavium/cn81xx/reset.c b/src/soc/cavium/cn81xx/reset.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d3be7c9</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/cavium/cn81xx/reset.c</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/addressmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void do_soft_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ write64((void *)RST_SOFT_RESET, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28022">change 28022</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad </div>
<div style="display:none"> Gerrit-Change-Number: 28022 </div>
<div style="display:none"> Gerrit-PatchSet: 8 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>