<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28340">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()<br><br>Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL,<br>which was deprecated in favor of a public PCI register (though only the<br>bits to enable debug port became public) 0x90. Therefor code needs to be<br>updated.<br><br>BUG=b:69231009<br>TEST=Build and boot grunt.<br><br>Change-Id: Ic10c43cb6e5a9e8fe3bccf79a8ed69a6a0b49fce<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/enable_usbdebug.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>2 files changed, 20 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28340/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>index efe34e5..a2b5dd5 100644</span><br><span>--- a/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>@@ -22,8 +22,6 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include <soc/southbridge.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define DEBUGPORT_MISC_CONTROL 0x80</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)</span><br><span> {</span><br><span> /* Enable all of the USB controllers */</span><br><span>@@ -38,15 +36,22 @@</span><br><span> return PCI_DEV(0, 0x12, 0);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Stoneyridge selects port 1 as the debug port by default, and coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+ * function usbdebug_init_() also selects port 1 if USBDEBUG_DEFAULT_PORT</span><br><span style="color: hsl(120, 100%, 40%);">+ * is not selected or set to 0. So if port 1 is used, no change is needed.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For ports 2 and 3, value of USBDEBUG_DEFAULT_PORT is the port itself,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but to work around usbdebug_init_(), if port 0 is desired set</span><br><span style="color: hsl(120, 100%, 40%);">+ * USBDEBUG_DEFAULT_PORT to 4.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 *base_regs = pci_ehci_base_regs(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32, value;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~(0xf << 28);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= (port << 28);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ value = (port & 0x00000003) << DEBUG_PORT_SELECT_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ value |= DEBUG_PORT_ENABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~DEBUG_PORT_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= value;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32);</span><br><span> }</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 530b93a..f054b3b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -305,6 +305,11 @@</span><br><span> #define OC_PORT2_SHIFT 8</span><br><span> #define OC_PORT3_SHIFT 12</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define EHCI_HUB_CONFIG4 0x90</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEBUG_PORT_SELECT_SHIFT 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEBUG_PORT_ENABLE BIT(18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define WIDEIO_RANGE_ERROR -1</span><br><span> #define TOTAL_WIDEIO_PORTS 3</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28340">change 28340</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic10c43cb6e5a9e8fe3bccf79a8ed69a6a0b49fce </div>
<div style="display:none"> Gerrit-Change-Number: 28340 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>