<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28282">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Make eMMC max speed configurable<br><br>The eMMC maximum speed is set to HS400 mode per default. To increase the<br>lifetime of the circuit, it is necessary to reduce the eMMC speed.<br><br>Change-Id: I6fa5eb56a0593e24269ef143645c506232879889<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/soc/intel/apollolake/chip.c<br>M src/soc/intel/apollolake/chip.h<br>2 files changed, 7 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28282/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index 83a6baa..f6595ce 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -2,7 +2,7 @@</span><br><span>  * This file is part of the coreboot project.</span><br><span>  *</span><br><span>  * Copyright (C) 2015 - 2017 Intel Corp.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Siemens AG</span><br><span>  * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)</span><br><span>  * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)</span><br><span>  *</span><br><span>@@ -616,6 +616,8 @@</span><br><span>          silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;</span><br><span>        if (cfg->emmc_rx_cmd_data_cntl2 != 0)</span><br><span>             silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;</span><br><span style="color: hsl(120, 100%, 40%);">+    if (cfg->emmc_host_max_speed != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+         silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed;</span><br><span> </span><br><span>    silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;</span><br><span> </span><br><span>diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h</span><br><span>index 61ddeda..f1384ad 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.h</span><br><span>+++ b/src/soc/intel/apollolake/chip.h</span><br><span>@@ -2,7 +2,7 @@</span><br><span>  * This file is part of the coreboot project.</span><br><span>  *</span><br><span>  * Copyright (C) 2015 Intel Corp.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Siemens AG</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Siemens AG</span><br><span>  * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>@@ -93,6 +93,9 @@</span><br><span>          */</span><br><span>  uint32_t emmc_rx_cmd_data_cntl2;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+  /* Select the eMMC max Speed allowed. */</span><br><span style="color: hsl(120, 100%, 40%);">+      uint8_t emmc_host_max_speed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>       /* Specifies on which IRQ the SCI will internally appear. */</span><br><span>         uint8_t sci_irq;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28282">change 28282</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28282"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6fa5eb56a0593e24269ef143645c506232879889 </div>
<div style="display:none"> Gerrit-Change-Number: 28282 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>