<p><a href="https://review.coreboot.org/28289">View Change</a></p><p>19 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c">File util/msrtool/intel_atom.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@800">Patch Set #1, Line 800:</a> <code style="font-family:monospace,monospace">                           conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@802">Patch Set #1, Line 802:</a> <code style="font-family:monospace,monospace">                          occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@823">Patch Set #1, Line 823:</a> <code style="font-family:monospace,monospace">                                conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@825">Patch Set #1, Line 825:</a> <code style="font-family:monospace,monospace">                          occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@846">Patch Set #1, Line 846:</a> <code style="font-family:monospace,monospace">                                conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_atom.c@848">Patch Set #1, Line 848:</a> <code style="font-family:monospace,monospace">                          occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c">File util/msrtool/intel_core2_later.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@824">Patch Set #1, Line 824:</a> <code style="font-family:monospace,monospace">                                conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@826">Patch Set #1, Line 826:</a> <code style="font-family:monospace,monospace">                           occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@847">Patch Set #1, Line 847:</a> <code style="font-family:monospace,monospace">                         conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@849">Patch Set #1, Line 849:</a> <code style="font-family:monospace,monospace">                           occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@870">Patch Set #1, Line 870:</a> <code style="font-family:monospace,monospace">                         conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_core2_later.c@872">Patch Set #1, Line 872:</a> <code style="font-family:monospace,monospace">                           occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c">File util/msrtool/intel_nehalem.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1112">Patch Set #1, Line 1112:</a> <code style="font-family:monospace,monospace">                  { MSR1(1), "CPU switch to the Minimum Enhanced Intel \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Avoid line continuations in quoted strings</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1376">Patch Set #1, Line 1376:</a> <code style="font-family:monospace,monospace">                              conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1378">Patch Set #1, Line 1378:</a> <code style="font-family:monospace,monospace">                             occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1399">Patch Set #1, Line 1399:</a> <code style="font-family:monospace,monospace">                           conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1401">Patch Set #1, Line 1401:</a> <code style="font-family:monospace,monospace">                             occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1422">Patch Set #1, Line 1422:</a> <code style="font-family:monospace,monospace">                           conditions occurring in the logical processor which programmed the MSR" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/28289/1/util/msrtool/intel_nehalem.c@1424">Patch Set #1, Line 1424:</a> <code style="font-family:monospace,monospace">                             occurring across all logical processors sharing a processor core" },</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/28289">change 28289</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28289"/><meta itemprop="name" content="View Change"/></div></div>

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<div style="display:none"> Gerrit-Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5 </div>
<div style="display:none"> Gerrit-Change-Number: 28289 </div>
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<div style="display:none"> Gerrit-Comment-Date: Thu, 23 Aug 2018 16:26:55 +0000 </div>
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