<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28286">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">fsp/fsp2_0/coffeelake: Update CFL FSP headers<br><br>Coffeelake FSP headers had been updated to version 7.0.3D.60, also<br>include a short script to download from github location and run dos2unix<br>for coreboot. Original file location from<br>https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg/Include.<br><br>BUG=N/A<br>TEST=Build and flash, able to boot up into OS on whiskeylake rvp<br>platform.<br><br>Change-Id: I656da83e9042642576b785643e423ba47da8dd73<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>A src/vendorcode/intel/fsp/fsp2_0/coffeelake/CFLFspHeaderUpdate.sh<br>M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h<br>3 files changed, 3,362 insertions(+), 3,241 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28286/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/CFLFspHeaderUpdate.sh b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/CFLFspHeaderUpdate.sh</span><br><span>new file mode 100755</span><br><span>index 0000000..8e291e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/CFLFspHeaderUpdate.sh</span><br><span>@@ -0,0 +1,11 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#!/bin/sh</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+rm FspmUpd.h FspsUpd.h</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+wget https://raw.githubusercontent.com/IntelFsp/FSP/master/CoffeeLakeFspBinPkg/Include/FspmUpd.h</span><br><span style="color: hsl(120, 100%, 40%);">+wget https://raw.githubusercontent.com/IntelFsp/FSP/master/CoffeeLakeFspBinPkg/Include/FspsUpd.h</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+dos2unix FspmUpd.h</span><br><span style="color: hsl(120, 100%, 40%);">+dos2unix FspmUpd.h</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h</span><br><span>index bfe581b..5a1580c 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h</span><br><span>@@ -37,19 +37,19 @@</span><br><span> </span><br><span> #pragma pack(1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-
</span><br><span style="color: hsl(0, 100%, 40%);">-#include <MemInfoHob.h>
</span><br><span style="color: hsl(0, 100%, 40%);">-
</span><br><span style="color: hsl(0, 100%, 40%);">-///
</span><br><span style="color: hsl(0, 100%, 40%);">-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
</span><br><span style="color: hsl(0, 100%, 40%);">-///
</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {
</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Revision; ///< Chipset Init Info Revision
</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Rsvd[3]; ///< Reserved
</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
</span><br><span style="color: hsl(0, 100%, 40%);">-} CHIPSET_INIT_INFO;
</span><br><span style="color: hsl(0, 100%, 40%);">-
</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <MemInfoHob.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.</span><br><span style="color: hsl(120, 100%, 40%);">+///</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision; ///< Chipset Init Info Revision</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Rsvd[3]; ///< Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table</span><br><span style="color: hsl(120, 100%, 40%);">+} CHIPSET_INIT_INFO;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span> /** Fsp M Configuration</span><br><span> **/</span><br><span>@@ -331,9 +331,16 @@</span><br><span> **/</span><br><span> UINT8 ScramblerSupport;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00C8</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C8 - Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ When this is skipped, boot loader must initialize processors before SilicionInit</span><br><span style="color: hsl(120, 100%, 40%);">+ API. </b>0: Initialize; <b>1: Skip</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace1[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipMpInit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C9</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[15];</span><br><span> </span><br><span> /** Offset 0x00D8 - SPD Profile Selected</span><br><span> Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP</span><br><span>@@ -479,7 +486,9 @@</span><br><span> UINT8 CpuTraceHubMemReg1Size;</span><br><span> </span><br><span> /** Offset 0x00F6 - Enable or Disable Peci C10 Reset command</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message</span><br><span style="color: hsl(120, 100%, 40%);">+ to disable peci reset on C10 exit. The default value is <b>0: Disable</b> for CNL,</span><br><span style="color: hsl(120, 100%, 40%);">+ and <b>1: Enable</b> for all other CPU's</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 PeciC10Reset;</span><br><span>@@ -949,7 +958,7 @@</span><br><span> </span><br><span> /** Offset 0x0205 - Maximum Core Turbo Ratio Override</span><br><span> Maximum core turbo ratio override allows to increase CPU core frequency beyond the</span><br><span style="color: hsl(0, 100%, 40%);">- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83</span><br><span style="color: hsl(120, 100%, 40%);">+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255</span><br><span> **/</span><br><span> UINT8 CoreMaxOcRatio;</span><br><span> </span><br><span>@@ -959,13 +968,15 @@</span><br><span> **/</span><br><span> UINT8 CoreVoltageMode;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0207</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0207 - Program Cache Attributes</span><br><span style="color: hsl(120, 100%, 40%);">+ Program Cache Attributes; <b>0: Program</b>; 1: Disable Program.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace6;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableMtrrProgram;</span><br><span> </span><br><span> /** Offset 0x0208 - Maximum clr turbo ratio override</span><br><span> Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the</span><br><span style="color: hsl(0, 100%, 40%);">- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83</span><br><span style="color: hsl(120, 100%, 40%);">+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255</span><br><span> **/</span><br><span> UINT8 RingMaxOcRatio;</span><br><span> </span><br><span>@@ -1116,7 +1127,7 @@</span><br><span> </span><br><span> /** Offset 0x0227</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace7;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace6;</span><br><span> </span><br><span> /** Offset 0x0228 - PrmrrSize</span><br><span> 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000</span><br><span>@@ -1861,12 +1872,12 @@</span><br><span> UINT8 RhActProbability;</span><br><span> </span><br><span> /** Offset 0x04C1 - RAPL PL 2 WindowX</span><br><span style="color: hsl(0, 100%, 40%);">- Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)</span><br><span style="color: hsl(120, 100%, 40%);">+ Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)</span><br><span> **/</span><br><span> UINT8 RaplLim2WindX;</span><br><span> </span><br><span> /** Offset 0x04C2 - RAPL PL 2 WindowY</span><br><span style="color: hsl(0, 100%, 40%);">- Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)</span><br><span style="color: hsl(120, 100%, 40%);">+ Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)</span><br><span> **/</span><br><span> UINT8 RaplLim2WindY;</span><br><span> </span><br><span>@@ -1881,52 +1892,52 @@</span><br><span> UINT8 RaplLim1WindY;</span><br><span> </span><br><span> /** Offset 0x04C5 - RAPL PL 2 Power</span><br><span style="color: hsl(0, 100%, 40%);">- range[0;2^14-1]= [2047.875;0]in W, (224= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+ range[0;2^14-1]= [2047.875;0]in W, (222= Def)</span><br><span> **/</span><br><span> UINT16 RaplLim2Pwr;</span><br><span> </span><br><span> /** Offset 0x04C7 - RAPL PL 1 Power</span><br><span style="color: hsl(0, 100%, 40%);">- range[0;2^14-1]= [2047.875;0]in W, (224= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+ range[0;2^14-1]= [2047.875;0]in W, (0= Def)</span><br><span> **/</span><br><span> UINT16 RaplLim1Pwr;</span><br><span> </span><br><span> /** Offset 0x04C9 - Warm Threshold Ch0 Dimm0</span><br><span style="color: hsl(0, 100%, 40%);">- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255</span><br><span> **/</span><br><span> UINT8 WarmThresholdCh0Dimm0;</span><br><span> </span><br><span> /** Offset 0x04CA - Warm Threshold Ch0 Dimm1</span><br><span style="color: hsl(0, 100%, 40%);">- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255</span><br><span> **/</span><br><span> UINT8 WarmThresholdCh0Dimm1;</span><br><span> </span><br><span> /** Offset 0x04CB - Warm Threshold Ch1 Dimm0</span><br><span style="color: hsl(0, 100%, 40%);">- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255</span><br><span> **/</span><br><span> UINT8 WarmThresholdCh1Dimm0;</span><br><span> </span><br><span> /** Offset 0x04CC - Warm Threshold Ch1 Dimm1</span><br><span style="color: hsl(0, 100%, 40%);">- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255</span><br><span> **/</span><br><span> UINT8 WarmThresholdCh1Dimm1;</span><br><span> </span><br><span> /** Offset 0x04CD - Hot Threshold Ch0 Dimm0</span><br><span style="color: hsl(0, 100%, 40%);">- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255</span><br><span> **/</span><br><span> UINT8 HotThresholdCh0Dimm0;</span><br><span> </span><br><span> /** Offset 0x04CE - Hot Threshold Ch0 Dimm1</span><br><span style="color: hsl(0, 100%, 40%);">- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255</span><br><span> **/</span><br><span> UINT8 HotThresholdCh0Dimm1;</span><br><span> </span><br><span> /** Offset 0x04CF - Hot Threshold Ch1 Dimm0</span><br><span style="color: hsl(0, 100%, 40%);">- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255</span><br><span> **/</span><br><span> UINT8 HotThresholdCh1Dimm0;</span><br><span> </span><br><span> /** Offset 0x04D0 - Hot Threshold Ch1 Dimm1</span><br><span style="color: hsl(0, 100%, 40%);">- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255</span><br><span> **/</span><br><span> UINT8 HotThresholdCh1Dimm1;</span><br><span> </span><br><span>@@ -2072,7 +2083,7 @@</span><br><span> </span><br><span> /** Offset 0x04ED - Throttler CKEMin Timer</span><br><span> Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).</span><br><span style="color: hsl(0, 100%, 40%);">- Dfault is 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+ Default is 0x30</span><br><span> **/</span><br><span> UINT8 ThrtCkeMinTmr;</span><br><span> </span><br><span>@@ -2286,9 +2297,34 @@</span><br><span> **/</span><br><span> UINT8 DualDimmPerChannelBoardType;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0510</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population.</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable(Default)=0, Enable=1</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspmUpd[15];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Ddr4MixedUDimm2DpcLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0511 - CFL Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved FspmConfig CFL</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmUpdCfl[2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0513 - Memory Test on Warm Boot</span><br><span style="color: hsl(120, 100%, 40%);">+ Run Base Memory Test on Warm Boot</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemTestOnWarmBoot;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0514 - Throttler CKEMin Timer - LPDDR</span><br><span style="color: hsl(120, 100%, 40%);">+ Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T +</span><br><span style="color: hsl(120, 100%, 40%);">+ BYTE_LENGTH (4). Default is 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThrtCkeMinTmrLpddr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0515</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmUpd[10];</span><br><span> } FSP_M_CONFIG;</span><br><span> </span><br><span> /** Fsp M Test Configuration</span><br><span>@@ -2513,7 +2549,7 @@</span><br><span> </span><br><span> /** Offset 0x0579</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace9;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace8;</span><br><span> </span><br><span> /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization</span><br><span> Range: 0-65535, default is 1000. @warning Do not change from the default</span><br><span>@@ -2596,14 +2632,13 @@</span><br><span> UINT8 SmbusSpdWriteDisable;</span><br><span> </span><br><span> /** Offset 0x059B - ChipsetInit HECI message</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.</span><br><span style="color: hsl(0, 100%, 40%);">- If disabled, it prevents from sending ChipsetInit HECI message.</span><br><span style="color: hsl(120, 100%, 40%);">+ DEPRECATED</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 ChipsetInitMessage;</span><br><span> </span><br><span> /** Offset 0x059C - Bypass ChipsetInit sync reset.</span><br><span style="color: hsl(0, 100%, 40%);">- 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message.</span><br><span style="color: hsl(120, 100%, 40%);">+ DEPRECATED</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 BypassPhySyncReset;</span><br><span>@@ -2788,7 +2823,7 @@</span><br><span> </span><br><span> /** Offset 0x051F</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace8;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace7;</span><br><span> </span><br><span> /** Offset 0x0520</span><br><span> **/</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h</span><br><span>index ac4fd58..653e669 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h</span><br><span>@@ -1,42 +1,42 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/** @file</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(0, 100%, 40%);">-are permitted provided that the following conditions are met:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(0, 100%, 40%);">- list of conditions and the following disclaimer.</span><br><span style="color: hsl(0, 100%, 40%);">-* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(0, 100%, 40%);">- list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(0, 100%, 40%);">- other materials provided with the distribution.</span><br><span style="color: hsl(0, 100%, 40%);">-* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(0, 100%, 40%);">- be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(0, 100%, 40%);">- specific prior written permission.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(0, 100%, 40%);">- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(0, 100%, 40%);">- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(0, 100%, 40%);">- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(0, 100%, 40%);">- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(0, 100%, 40%);">- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(0, 100%, 40%);">- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(0, 100%, 40%);">- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(0, 100%, 40%);">- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(0, 100%, 40%);">- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(0, 100%, 40%);">- THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __FSPSUPD_H__</span><br><span style="color: hsl(0, 100%, 40%);">-#define __FSPSUPD_H__</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <FspUpd.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#pragma pack(1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,
</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this
</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.
</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this
</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or
</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.
</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may
</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without
</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPSUPD_H__
</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPSUPD_H__
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspUpd.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span> </span><br><span> ///
</span><br><span> /// Azalia Header structure
</span><br><span>@@ -80,3164 +80,3239 @@</span><br><span> </span><br><span> #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Fsp S Configuration</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0020 - Logo Pointer</span><br><span style="color: hsl(0, 100%, 40%);">- Points to PEI Display Logo Image</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 LogoPtr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0024 - Logo Size</span><br><span style="color: hsl(0, 100%, 40%);">- Size of PEI Display Logo Image</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 LogoSize;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0028 - Graphics Configuration Ptr</span><br><span style="color: hsl(0, 100%, 40%);">- Points to VBT</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 GraphicsConfigPtr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x002C - Enable Device 4</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable Device 4</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Device4Enable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x002D - Enable HD Audio DSP</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio DSP feature.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaDspEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x002E</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace0[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0031 - Enable eMMC Controller</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable eMMC Controller.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ScsEmmcEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0032 - Enable eMMC HS400 Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Enable eMMC HS400 Mode.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ScsEmmcHs400Enabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0033 - Enable SdCard Controller</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable SD Card Controller.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ScsSdCardEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0034 - Show SPI controller</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable to show SPI controller.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ShowSpiController;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0035</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace1[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0038 - MicrocodeRegionBase</span><br><span style="color: hsl(0, 100%, 40%);">- Memory Base of Microcode Updates</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 MicrocodeRegionBase;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x003C - MicrocodeRegionSize</span><br><span style="color: hsl(0, 100%, 40%);">- Size of Microcode Updates</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 MicrocodeRegionSize;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0040 - Turbo Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable Turbo mode. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TurboMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0041 - Enable SATA SALP Support</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable SATA Aggressive Link Power Management.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataSalpSupport;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0042 - Enable SATA ports</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,</span><br><span style="color: hsl(0, 100%, 40%);">- and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsEnable[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x004A - Enable SATA DEVSLP Feature</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each</span><br><span style="color: hsl(0, 100%, 40%);">- port, byte0 for port0, byte1 for port1, and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsDevSlp[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0052 - Enable USB2 ports</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for</span><br><span style="color: hsl(0, 100%, 40%);">- port1, and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PortUsb20Enable[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0062 - Enable USB3 ports</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for</span><br><span style="color: hsl(0, 100%, 40%);">- port1, and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PortUsb30Enable[10];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x006C - Enable xDCI controller</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable to xDCI controller.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 XdciEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x006D</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace2[2];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x006F - Enable SerialIo Device Mode</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable</span><br><span style="color: hsl(0, 100%, 40%);">- SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device</span><br><span style="color: hsl(0, 100%, 40%);">- mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1,</span><br><span style="color: hsl(0, 100%, 40%);">- and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SerialIoDevMode[12];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.</span><br><span style="color: hsl(0, 100%, 40%);">- The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 DevIntConfigPtr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x007F - Number of DevIntConfig Entry</span><br><span style="color: hsl(0, 100%, 40%);">- Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr</span><br><span style="color: hsl(0, 100%, 40%);">- must not be NULL.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 NumOfDevIntConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0080 - PIRQx to IRQx Map Config</span><br><span style="color: hsl(0, 100%, 40%);">- PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for</span><br><span style="color: hsl(0, 100%, 40%);">- PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy</span><br><span style="color: hsl(0, 100%, 40%);">- 8259 PCI mode.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PxRcConfig[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0088 - Select GPIO IRQ Route</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO IRQ Select. The valid value is 14 or 15.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 GpioIrqRoute;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0089 - Select SciIrqSelect</span><br><span style="color: hsl(0, 100%, 40%);">- SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SciIrqSelect;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x008A - Select TcoIrqSelect</span><br><span style="color: hsl(0, 100%, 40%);">- TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TcoIrqSelect;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x008B - Enable/Disable Tco IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable TCO IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TcoIrqEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x008C - PCH HDA Verb Table Entry Number</span><br><span style="color: hsl(0, 100%, 40%);">- Number of Entries in Verb Table.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaVerbTableEntryNum;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x008D - PCH HDA Verb Table Pointer</span><br><span style="color: hsl(0, 100%, 40%);">- Pointer to Array of pointers to Verb Table.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PchHdaVerbTablePtr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0091 - PCH HDA Codec Sx Wake Capability</span><br><span style="color: hsl(0, 100%, 40%);">- Capability to detect wake initiated by a codec in Sx</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaCodecSxWakeCapability;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0092 - Enable SATA</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable SATA controller.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0093 - SATA Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Select SATA controller working mode.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:AHCI, 1:RAID</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0094 - USB Per Port HS Preemphasis Bias</span><br><span style="color: hsl(0, 100%, 40%);">- USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,</span><br><span style="color: hsl(0, 100%, 40%);">- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb2AfePetxiset[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00A4 - USB Per Port HS Transmitter Bias</span><br><span style="color: hsl(0, 100%, 40%);">- USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,</span><br><span style="color: hsl(0, 100%, 40%);">- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb2AfeTxiset[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis</span><br><span style="color: hsl(0, 100%, 40%);">- USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,</span><br><span style="color: hsl(0, 100%, 40%);">- 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb2AfePredeemp[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis</span><br><span style="color: hsl(0, 100%, 40%);">- USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.</span><br><span style="color: hsl(0, 100%, 40%);">- One byte for each port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb2AfePehalfbit[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment</span><br><span style="color: hsl(0, 100%, 40%);">- Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value</span><br><span style="color: hsl(0, 100%, 40%);">- in arrary can be between 0-1. One byte for each port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb3HsioTxDeEmphEnable[10];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting</span><br><span style="color: hsl(0, 100%, 40%);">- USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],</span><br><span style="color: hsl(0, 100%, 40%);">- <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb3HsioTxDeEmph[10];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment</span><br><span style="color: hsl(0, 100%, 40%);">- Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value</span><br><span style="color: hsl(0, 100%, 40%);">- in arrary can be between 0-1. One byte for each port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb3HsioTxDownscaleAmpEnable[10];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment</span><br><span style="color: hsl(0, 100%, 40%);">- USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default</span><br><span style="color: hsl(0, 100%, 40%);">- = 00h</b>. One byte for each port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb3HsioTxDownscaleAmp[10];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00FC - Enable LAN</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable LAN controller.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchLanEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00FD - Enable HD Audio Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkHda;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00FE - Enable HD Audio DMIC0 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkDmic0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00FF - Enable HD Audio DMIC1 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkDmic1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0100 - Enable HD Audio SSP0 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkSsp0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0101 - Enable HD Audio SSP1 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkSsp1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0102 - Enable HD Audio SSP2 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio SSP2/I2S link.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkSsp2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0103 - Enable HD Audio SoundWire#1 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio SNDW1 link. Muxed with HDA.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkSndw1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0104 - Enable HD Audio SoundWire#2 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio SNDW2 link. Muxed with SSP1.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkSndw2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0105 - Enable HD Audio SoundWire#3 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkSndw3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0106 - Enable HD Audio SoundWire#4 Link</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaAudioLinkSndw4;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting</span><br><span style="color: hsl(0, 100%, 40%);">- 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaSndwBufferRcomp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0108 - PTM for PCIE RP Mask</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.</span><br><span style="color: hsl(0, 100%, 40%);">- One bit for each port, bit0 for port1, bit1 for port2, and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PcieRpPtmMask;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x010C - DPC for PCIE RP Mask</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.</span><br><span style="color: hsl(0, 100%, 40%);">- One bit for each port, bit0 for port1, bit1 for port2, and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PcieRpDpcMask;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0110 - DPC Extensions PCIE RP Mask</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit</span><br><span style="color: hsl(0, 100%, 40%);">- for each port, bit0 for port1, bit1 for port2, and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PcieRpDpcExtensionsMask;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0114 - USB PDO Programming</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming</span><br><span style="color: hsl(0, 100%, 40%);">- during later phase. 1: enable, 0: disable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UsbPdoProgramming;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0115 - Power button debounce configuration</span><br><span style="color: hsl(0, 100%, 40%);">- Debounce time for PWRBTN in microseconds. For values not supported by HW, they will</span><br><span style="color: hsl(0, 100%, 40%);">- be rounded down to closest supported on. 0: disable, 250-1024000us: supported range</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PmcPowerButtonDebounce;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0119 - PCH eSPI Master and Slave BME enabled</span><br><span style="color: hsl(0, 100%, 40%);">- PCH eSPI Master and Slave BME enabled</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchEspiBmeMasterSlaveEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x011A - PCH SATA use RST Legacy OROM</span><br><span style="color: hsl(0, 100%, 40%);">- Use PCH SATA RST Legacy OROM when CSM is Enabled</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstLegacyOrom;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x011B - Trace Hub Memory Base</span><br><span style="color: hsl(0, 100%, 40%);">- If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate</span><br><span style="color: hsl(0, 100%, 40%);">- trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub</span><br><span style="color: hsl(0, 100%, 40%);">- memory is configured properly.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 TraceHubMemBase;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x011F - PMC Debug Message Enable</span><br><span style="color: hsl(0, 100%, 40%);">- When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW</span><br><span style="color: hsl(0, 100%, 40%);">- will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PmcDbgMsgEn;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0120 - PchPostMemRsvd</span><br><span style="color: hsl(0, 100%, 40%);">- Reserved for PCH Post-Mem</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPostMemRsvd[37];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0145 - Enable Ufs Controller</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/disable Ufs 2.0 Controller.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ScsUfsEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0146 - CNVi Configuration</span><br><span style="color: hsl(0, 100%, 40%);">- This option allows for automatic detection of Connectivity Solution. [Auto Detection]</span><br><span style="color: hsl(0, 100%, 40%);">- assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disable, 1:Auto</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchCnviMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0147 - SdCard power enable polarity</span><br><span style="color: hsl(0, 100%, 40%);">- Choose SD_PWREN# polarity</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Active low, 1: Active high</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SdCardPowerEnableActiveHigh;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0148 - PCH USB2 PHY Power Gating enable</span><br><span style="color: hsl(0, 100%, 40%);">- 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY</span><br><span style="color: hsl(0, 100%, 40%);">- Sus Well PG</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchUsb2PhySusPgEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0149 - PCH USB OverCurrent mapping enable</span><br><span style="color: hsl(0, 100%, 40%);">- 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin</span><br><span style="color: hsl(0, 100%, 40%);">- mapping allow for NOA usage of OC pins</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchUsbOverCurrentEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x014A</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x014B - CNVi MfUart1 Type</span><br><span style="color: hsl(0, 100%, 40%);">- This option configures Uart type which connects to MfUart1</span><br><span style="color: hsl(0, 100%, 40%);">- 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchCnviMfUart1Type;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x014C - Espi Lgmr Memory Range decode</span><br><span style="color: hsl(0, 100%, 40%);">- This option enables or disables espi lgmr</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchEspiLgmrEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x014D - HECI3 state</span><br><span style="color: hsl(0, 100%, 40%);">- The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.</span><br><span style="color: hsl(0, 100%, 40%);">- 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Heci3Enabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x014E</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace4;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x014F - PCHHOT# pin</span><br><span style="color: hsl(0, 100%, 40%);">- Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHotEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0150 - SATA LED</span><br><span style="color: hsl(0, 100%, 40%);">- SATA LED indicating SATA controller activity. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataLedEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0151 - VRAlert# Pin</span><br><span style="color: hsl(0, 100%, 40%);">- When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling</span><br><span style="color: hsl(0, 100%, 40%);">- to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmVrAlert;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0152 - SLP_S0 VM Dynamic Control</span><br><span style="color: hsl(0, 100%, 40%);">- SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpS0VmRuntimeControl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0153 - SLP_S0 VM 0.70V Support</span><br><span style="color: hsl(0, 100%, 40%);">- SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpS0Vm070VSupport;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0154 - SLP_S0 VM 0.75V Support</span><br><span style="color: hsl(0, 100%, 40%);">- SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpS0Vm075VSupport;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0155 - AMT Switch</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 AmtEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0156 - WatchDog Timer Switch</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 WatchDog;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0157 - ASF Switch</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 AsfEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0158 - Manageability Mode set by Mebx</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ManageabilityMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0159 - PET Progress</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive</span><br><span style="color: hsl(0, 100%, 40%);">- PET Events.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 FwProgress;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x015A - SOL Switch</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 AmtSolEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x015B - OS Timer</span><br><span style="color: hsl(0, 100%, 40%);">- 16 bits Value, Set OS watchdog timer.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 WatchDogTimerOs;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x015D - BIOS Timer</span><br><span style="color: hsl(0, 100%, 40%);">- 16 bits Value, Set BIOS watchdog timer.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 WatchDogTimerBios;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x015F - Remote Assistance Trigger Availablilty</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 RemoteAssistance;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0160 - KVM Switch</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 AmtKvmEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0161 - KVM Switch</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ForcMebxSyncUp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0162</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace5[1];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0163 - PCH PCIe root port connection type</span><br><span style="color: hsl(0, 100%, 40%);">- 0: built-in device, 1:slot</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpSlotImplemented[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x017B - Usage type for ClkSrc</span><br><span style="color: hsl(0, 100%, 40%);">- 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use</span><br><span style="color: hsl(0, 100%, 40%);">- (free running), 0xFF: not used</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieClkSrcUsage[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x018B - ClkReq-to-ClkSrc mapping</span><br><span style="color: hsl(0, 100%, 40%);">- Number of ClkReq signal assigned to ClkSrc</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieClkSrcClkReq[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x019B - PCIE RP Access Control Services Extended Capability</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable PCIE RP Access Control Services Extended Capability</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpAcsEnabled[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x01B3 - PCIE RP Clock Power Management</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal</span><br><span style="color: hsl(0, 100%, 40%);">- can still be controlled by L1 PM substates mechanism</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpEnableCpm[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x01CB - PCIE RP Detect Timeout Ms</span><br><span style="color: hsl(0, 100%, 40%);">- The number of milliseconds within 0~65535 in reference code will wait for link to</span><br><span style="color: hsl(0, 100%, 40%);">- exit Detect state for enabled ports before assuming there is no device and potentially</span><br><span style="color: hsl(0, 100%, 40%);">- disabling the port.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PcieRpDetectTimeoutMs[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on</span><br><span style="color: hsl(0, 100%, 40%);">- PCH-H. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PmcModPhySusPgEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x01FC - SlpS0WithGbeSupport</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SlpS0WithGbeSupport;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x01FD</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace6[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0200 - Enable/Disable SA CRID</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: SA CRID, Disable (Default): SA CRID</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CridEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0201 - DMI ASPM</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disable, 1:L0s, 2:L1, 3:L0sL1</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DmiAspm;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0202 - PCIe DeEmphasis control per root port</span><br><span style="color: hsl(0, 100%, 40%);">- 0: -6dB, 1(Default): -3.5dB</span><br><span style="color: hsl(0, 100%, 40%);">- 0:-6dB, 1:-3.5dB</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PegDeEmphasis[4];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0206 - PCIe Slot Power Limit value per root port</span><br><span style="color: hsl(0, 100%, 40%);">- Slot power limit value per root port</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PegSlotPowerLimitValue[4];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x020A - PCIe Slot Power Limit scale per root port</span><br><span style="color: hsl(0, 100%, 40%);">- Slot power limit scale per root port</span><br><span style="color: hsl(0, 100%, 40%);">- 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PegSlotPowerLimitScale[4];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x020E - PCIe Physical Slot Number per root port</span><br><span style="color: hsl(0, 100%, 40%);">- Physical Slot Number per root port</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PegPhysicalSlotNumber[4];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0216 - Enable/Disable PavpEnable</span><br><span style="color: hsl(0, 100%, 40%);">- Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PavpEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0217 - CdClock Frequency selection</span><br><span style="color: hsl(0, 100%, 40%);">- 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz</span><br><span style="color: hsl(0, 100%, 40%);">- 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CdClock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PeiGraphicsPeimInit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0219</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace7;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x021A - Enable or disable GNA device</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 GnaEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable/Clear, 1=Enable/Set</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 X2ApicOptOut;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x021C - Base addresses for VT-d function MMIO access</span><br><span style="color: hsl(0, 100%, 40%);">- Base addresses for VT-d MMIO access per VT-d engine</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 VtdBaseAddress[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0228 - Enable or disable eDP device</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortEdp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0229 - Enable or disable HPD of DDI port B</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortBHpd;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x022A - Enable or disable HPD of DDI port C</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortCHpd;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x022B - Enable or disable HPD of DDI port D</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortDHpd;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x022C - Enable or disable HPD of DDI port F</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortFHpd;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x022D - Enable or disable DDC of DDI port B</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortBDdc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x022E - Enable or disable DDC of DDI port C</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortCDdc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x022F - Enable or disable DDC of DDI port D</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortDDdc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0230 - Enable or disable DDC of DDI port F</span><br><span style="color: hsl(0, 100%, 40%);">- 0(Default)=Disable, 1=Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DdiPortFDdc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0231 - Enable/Disable SkipS3CdClockInit</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full</span><br><span style="color: hsl(0, 100%, 40%);">- CD clock in S3 resume due to GOP absent</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SkipS3CdClockInit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms</span><br><span style="color: hsl(0, 100%, 40%);">- Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate</span><br><span style="color: hsl(0, 100%, 40%);">- T12 Delay to max 500ms</span><br><span style="color: hsl(0, 100%, 40%);">- 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 DeltaT12PowerCycleDelay;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0234 - Blt Buffer Address</span><br><span style="color: hsl(0, 100%, 40%);">- Address of Blt buffer</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 BltBufferAddress;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0238 - Blt Buffer Size</span><br><span style="color: hsl(0, 100%, 40%);">- Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_GRAPHICS_OUTPUT_BLT_PIXEL)</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 BltBufferSize;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x023C - SaPostMemProductionRsvd</span><br><span style="color: hsl(0, 100%, 40%);">- Reserved for SA Post-Mem Production</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SaPostMemProductionRsvd[35];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for</span><br><span style="color: hsl(0, 100%, 40%);">- Alpine ridge</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRootPortGen2PllL1CgDisable[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0277 - Advanced Encryption Standard (AES) feature</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 AesEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0278 - Power State 3 enable/disable</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- For all VR Indexes</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Psi3Enable[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x027D - Power State 4 enable/disable</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For</span><br><span style="color: hsl(0, 100%, 40%);">- all VR Indexes</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Psi4Enable[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0282 - Imon slope correction</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.</span><br><span style="color: hsl(0, 100%, 40%);">- Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ImonSlope[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0287 - Imon offset correction</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.</span><br><span style="color: hsl(0, 100%, 40%);">- Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b></span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ImonOffset[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x028C - Enable/Disable BIOS configuration of VR</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 VrConfigEnable[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0291 - Thermal Design Current enable/disable</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:</span><br><span style="color: hsl(0, 100%, 40%);">- Enable.For all VR Indexes</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TdcEnable[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0296 - HECI3 state</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.</span><br><span style="color: hsl(0, 100%, 40%);">- Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms</span><br><span style="color: hsl(0, 100%, 40%);">- , 8 - 8ms , 10 - 10ms.For all VR Indexe</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TdcTimeWindow[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x029B - Thermal Design Current Lock</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For</span><br><span style="color: hsl(0, 100%, 40%);">- all VR Indexes</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TdcLock[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02A0 - Platform Psys slope correction</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in</span><br><span style="color: hsl(0, 100%, 40%);">- 1/100 increment values. Range is 0-200. 125 = 1.25</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PsysSlope;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02A1 - Platform Psys offset correction</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0-255. Value of 100 = 100/4 = 25 offset</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PsysOffset;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02A2 - Acoustic Noise Mitigation feature</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 AcousticNoiseMitigation;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain</span><br><span style="color: hsl(0, 100%, 40%);">- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation</span><br><span style="color: hsl(0, 100%, 40%);">- feature enabled. <b>0: False</b>; 1: True</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 FastPkgCRampDisableIa;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain</span><br><span style="color: hsl(0, 100%, 40%);">- Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic</span><br><span style="color: hsl(0, 100%, 40%);">- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SlowSlewRateForIa;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain</span><br><span style="color: hsl(0, 100%, 40%);">- Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic</span><br><span style="color: hsl(0, 100%, 40%);">- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SlowSlewRateForGt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain</span><br><span style="color: hsl(0, 100%, 40%);">- Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic</span><br><span style="color: hsl(0, 100%, 40%);">- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SlowSlewRateForSa;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02A7 - Thermal Design Current current limit</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.</span><br><span style="color: hsl(0, 100%, 40%);">- Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 TdcPowerLimit[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02B1 - AcLoadline</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is</span><br><span style="color: hsl(0, 100%, 40%);">- 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 AcLoadline[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02BB</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace8[10];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02C5 - DcLoadline</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is</span><br><span style="color: hsl(0, 100%, 40%);">- 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b></span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 DcLoadline[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02CF - Power State 1 Threshold current</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 Psi1Threshold[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02D9 - Power State 2 Threshold current</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 Psi2Threshold[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02E3 - Power State 3 Threshold current</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 Psi3Threshold[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02ED - Icc Max limit</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 IccMax[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x02F7 - VR Voltage Limit</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 VrVoltageLimit[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain</span><br><span style="color: hsl(0, 100%, 40%);">- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation</span><br><span style="color: hsl(0, 100%, 40%);">- feature enabled. <b>0: False</b>; 1: True</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 FastPkgCRampDisableGt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain</span><br><span style="color: hsl(0, 100%, 40%);">- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation</span><br><span style="color: hsl(0, 100%, 40%);">- feature enabled. <b>0: False</b>; 1: True</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 FastPkgCRampDisableSa;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0303 - Enable VR specific mailbox command</span><br><span style="color: hsl(0, 100%, 40%);">- VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A</span><br><span style="color: hsl(0, 100%, 40%);">- VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific</span><br><span style="color: hsl(0, 100%, 40%);">- command sent for PS4 exit issue. 11b - Reserved.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SendVrMbxCmd;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0304 - Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- Reserved</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Reserved2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0305 - Enable or Disable TXT</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TxtEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0306</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace9[6];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x030C - Skip Multi-Processor Initialization</span><br><span style="color: hsl(0, 100%, 40%);">- When this is skipped, boot loader must initialize processors before SilicionInit</span><br><span style="color: hsl(0, 100%, 40%);">- API. </b>0: Initialize; <b>1: Skip</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SkipMpInit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x030D - McIVR RFI Frequency Prefix</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:</span><br><span style="color: hsl(0, 100%, 40%);">- Minus (-).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 McivrRfiFrequencyPrefix;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x030E - McIVR RFI Frequency Adjustment</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in</span><br><span style="color: hsl(0, 100%, 40%);">- increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 McivrRfiFrequencyAdjust;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x030F - FIVR RFI Frequency</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:</span><br><span style="color: hsl(0, 100%, 40%);">- Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;</span><br><span style="color: hsl(0, 100%, 40%);">- 0-1535 (Up to 153.5MHz) for 19MHz clock.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 FivrRfiFrequency;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0311 - McIVR RFI Spread Spectrum</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-</span><br><span style="color: hsl(0, 100%, 40%);">- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 McivrSpreadSpectrum;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0312 - FIVR RFI Spread Spectrum</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;</span><br><span style="color: hsl(0, 100%, 40%);">- Range: 0.0% to 10.0% (0-100).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 FivrSpreadSpectrum;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain</span><br><span style="color: hsl(0, 100%, 40%);">- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation</span><br><span style="color: hsl(0, 100%, 40%);">- feature enabled. <b>0: False</b>; 1: True</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 FastPkgCRampDisableFivr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain</span><br><span style="color: hsl(0, 100%, 40%);">- Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic</span><br><span style="color: hsl(0, 100%, 40%);">- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SlowSlewRateForFivr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0315 - CpuBistData</span><br><span style="color: hsl(0, 100%, 40%);">- Pointer CPU BIST Data</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 CpuBistData;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.</span><br><span style="color: hsl(0, 100%, 40%);">- Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox</span><br><span style="color: hsl(0, 100%, 40%);">- command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 IslVrCmd;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x031A - Imon slope1 correction</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.</span><br><span style="color: hsl(0, 100%, 40%);">- Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 ImonSlope1[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0324 - CPU VR Power Delivery Design</span><br><span style="color: hsl(0, 100%, 40%);">- Used to communicate the power delivery design capability of the board. This value</span><br><span style="color: hsl(0, 100%, 40%);">- is an enum of the available power delivery segments that are defined in the Platform</span><br><span style="color: hsl(0, 100%, 40%);">- Design Guide.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 VrPowerDeliveryDesign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0328 - ReservedCpuPostMemProduction</span><br><span style="color: hsl(0, 100%, 40%);">- Reserved for CPU Post-Mem Production</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedCpuPostMemProduction[1];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0329</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace10[29];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0346 - Enable DMI ASPM</span><br><span style="color: hsl(0, 100%, 40%);">- Deprecated.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchDmiAspm;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0347 - Enable Power Optimizer</span><br><span style="color: hsl(0, 100%, 40%);">- Enable DMI Power Optimizer on PCH side.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPwrOptEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0348 - PCH Flash Protection Ranges Write Enble</span><br><span style="color: hsl(0, 100%, 40%);">- Write or erase is blocked by hardware.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchWriteProtectionEnable[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x034D - PCH Flash Protection Ranges Read Enble</span><br><span style="color: hsl(0, 100%, 40%);">- Read is blocked by hardware.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchReadProtectionEnable[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0352 - PCH Protect Range Limit</span><br><span style="color: hsl(0, 100%, 40%);">- Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for</span><br><span style="color: hsl(0, 100%, 40%);">- limit comparison.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PchProtectedRangeLimit[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x035C - PCH Protect Range Base</span><br><span style="color: hsl(0, 100%, 40%);">- Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PchProtectedRangeBase[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0366 - Enable Pme</span><br><span style="color: hsl(0, 100%, 40%);">- Enable Azalia wake-on-ring.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaPme;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0367</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace11;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0368 - VC Type</span><br><span style="color: hsl(0, 100%, 40%);">- Virtual Channel Type Select: 0: VC0, 1: VC1.</span><br><span style="color: hsl(0, 100%, 40%);">- 0: VC0, 1: VC1</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaVcType;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0369 - HD Audio Link Frequency</span><br><span style="color: hsl(0, 100%, 40%);">- HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.</span><br><span style="color: hsl(0, 100%, 40%);">- 0: 6MHz, 1: 12MHz, 2: 24MHz</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaLinkFrequency;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x036A - iDisp-Link Frequency</span><br><span style="color: hsl(0, 100%, 40%);">- iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.</span><br><span style="color: hsl(0, 100%, 40%);">- 4: 96MHz, 3: 48MHz</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaIDispLinkFrequency;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x036B - iDisp-Link T-mode</span><br><span style="color: hsl(0, 100%, 40%);">- iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.</span><br><span style="color: hsl(0, 100%, 40%);">- 0: 2T, 1: 1T</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaIDispLinkTmode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox</span><br><span style="color: hsl(0, 100%, 40%);">- driver or SST driver supported).</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaDspUaaCompliance;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x036D - iDisplay Audio Codec disconnection</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchHdaIDispCodecDisconnect;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x036E</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace12[15];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x037D - Enable PCH Io Apic Entry 24-119</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIoApicEntry24_119;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x037E - PCH Io Apic ID</span><br><span style="color: hsl(0, 100%, 40%);">- This member determines IOAPIC ID. Default is 0x02.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIoApicId;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x037F</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace13;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshSpiGpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshUart0GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshUart1GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshI2c0GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshI2c1GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshI2c2GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshGp0GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshGp1GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshGp2GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshGp3GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshGp4GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshGp5GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshGp6GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshGp7GpioAssign;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x038E - PCH ISH PDT Unlock Msg</span><br><span style="color: hsl(0, 100%, 40%);">- 0: False; 1: True.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchIshPdtUnlock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchLanLtrEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0390</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace14[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK</span><br><span style="color: hsl(0, 100%, 40%);">- Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region</span><br><span style="color: hsl(0, 100%, 40%);">- protection.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchLockDownBiosLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0394 - PCH Compatibility Revision ID</span><br><span style="color: hsl(0, 100%, 40%);">- This member describes whether or not the CRID feature of PCH should be enabled.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchCrid;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0395 - RTC CMOS MEMORY LOCK</span><br><span style="color: hsl(0, 100%, 40%);">- Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper</span><br><span style="color: hsl(0, 100%, 40%);">- and and lower 128-byte bank of RTC RAM.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchLockDownRtcMemoryLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0396 - Enable PCIE RP HotPlug</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the root port is hot plug available.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpHotPlug[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03AE - Enable PCIE RP Pm Sci</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the root port power manager SCI is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpPmSci[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03C6 - Enable PCIE RP Ext Sync</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the extended synch is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpExtSync[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the Transmitter Half Swing is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpTransmitterHalfSwing[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03F6 - Enable PCIE RP Clk Req Detect</span><br><span style="color: hsl(0, 100%, 40%);">- Probe CLKREQ# signal before enabling CLKREQ# based power management.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpClkReqDetect[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x040E - PCIE RP Advanced Error Report</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the Advanced Error Reporting is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpAdvancedErrorReporting[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0426 - PCIE RP Unsupported Request Report</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the Unsupported Request Report is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpUnsupportedRequestReport[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x043E - PCIE RP Fatal Error Report</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the Fatal Error Report is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpFatalErrorReport[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0456 - PCIE RP No Fatal Error Report</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the No Fatal Error Report is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpNoFatalErrorReport[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x046E - PCIE RP Correctable Error Report</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the Correctable Error Report is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpCorrectableErrorReport[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0486 - PCIE RP System Error On Fatal Error</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the System Error on Fatal Error is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpSystemErrorOnFatalError[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x049E - PCIE RP System Error On Non Fatal Error</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the System Error on Non Fatal Error is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpSystemErrorOnNonFatalError[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x04B6 - PCIE RP System Error On Correctable Error</span><br><span style="color: hsl(0, 100%, 40%);">- Indicate whether the System Error on Correctable Error is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpSystemErrorOnCorrectableError[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x04CE - PCIE RP Max Payload</span><br><span style="color: hsl(0, 100%, 40%);">- Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpMaxPayload[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x04E6</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace15[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x04FE - PCIE RP Pcie Speed</span><br><span style="color: hsl(0, 100%, 40%);">- Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_PCIE_SPEED).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpPcieSpeed[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method</span><br><span style="color: hsl(0, 100%, 40%);">- PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;</span><br><span style="color: hsl(0, 100%, 40%);">- 1: hardware equalization; 4: Fixed Coeficients.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpGen3EqPh3Method[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x052E - PCIE RP Physical Slot Number</span><br><span style="color: hsl(0, 100%, 40%);">- Indicates the slot number for the root port. Default is the value as root port index.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpPhysicalSlotNumber[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0546 - PCIE RP Completion Timeout</span><br><span style="color: hsl(0, 100%, 40%);">- The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpCompletionTimeout[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x055E</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace16[106];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x05C8 - PCIE RP Aspm</span><br><span style="color: hsl(0, 100%, 40%);">- The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is</span><br><span style="color: hsl(0, 100%, 40%);">- PchPcieAspmAutoConfig.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpAspm[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x05E0 - PCIE RP L1 Substates</span><br><span style="color: hsl(0, 100%, 40%);">- The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).</span><br><span style="color: hsl(0, 100%, 40%);">- Default is PchPcieL1SubstatesL1_1_2.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpL1Substates[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x05F8 - PCIE RP Ltr Enable</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting Mechanism.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpLtrEnable[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0610 - PCIE RP Ltr Config Lock</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpLtrConfigLock[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieEqPh3LaneParamCm[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieEqPh3LaneParamCp[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0658 - PCIE Sw Eq CoeffList Cm</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_PCIE_EQ_PARAM. Coefficient C-1.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieSwEqCoeffListCm[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x065D - PCIE Sw Eq CoeffList Cp</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_PCIE_EQ_PARAM. Coefficient C+1.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieSwEqCoeffListCp[5];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0662 - PCIE Disable RootPort Clock Gating</span><br><span style="color: hsl(0, 100%, 40%);">- Describes whether the PCI Express Clock Gating for each root port is enabled by</span><br><span style="color: hsl(0, 100%, 40%);">- platform modules. 0: Disable; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieDisableRootPortClockGating;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0663 - PCIE Enable Peer Memory Write</span><br><span style="color: hsl(0, 100%, 40%);">- This member describes whether Peer Memory Writes are enabled on the platform.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieEnablePeerMemoryWrite;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0664</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace17;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0665 - PCIE Compliance Test Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Compliance Test Mode shall be enabled when using Compliance Load Board.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieComplianceTestMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0666 - PCIE Rp Function Swap</span><br><span style="color: hsl(0, 100%, 40%);">- Allows BIOS to use root port function number swapping when root port of function</span><br><span style="color: hsl(0, 100%, 40%);">- 0 is disabled.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpFunctionSwap;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0667</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace18[2];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS</span><br><span style="color: hsl(0, 100%, 40%);">- When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmPmeB0S5Dis;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x066A - SPI ChipSelect signal polarity</span><br><span style="color: hsl(0, 100%, 40%);">- Selects SPI ChipSelect signal polarity.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SerialIoSpiCsPolarity[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x066D - PCIE IMR</span><br><span style="color: hsl(0, 100%, 40%);">- Enables Isolated Memory Region for PCIe.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpImrEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x066E - PCIE IMR port number</span><br><span style="color: hsl(0, 100%, 40%);">- Selects PCIE root port number for IMR feature.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpImrSelection;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x066F</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace19;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0670 - PCH Pm Wol Enable Override</span><br><span style="color: hsl(0, 100%, 40%);">- Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmWolEnableOverride;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx</span><br><span style="color: hsl(0, 100%, 40%);">- Determine if enable PCIe to wake from deep Sx.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmPcieWakeFromDeepSx;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0672 - PCH Pm WoW lan Enable</span><br><span style="color: hsl(0, 100%, 40%);">- Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmWoWlanEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable</span><br><span style="color: hsl(0, 100%, 40%);">- Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the</span><br><span style="color: hsl(0, 100%, 40%);">- PWRM_CFG3 register.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmWoWlanDeepSxEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0674 - PCH Pm Lan Wake From DeepSx</span><br><span style="color: hsl(0, 100%, 40%);">- Determine if enable LAN to wake from deep Sx.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmLanWakeFromDeepSx;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0675 - PCH Pm Deep Sx Pol</span><br><span style="color: hsl(0, 100%, 40%);">- Deep Sx Policy.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmDeepSxPol;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0676 - PCH Pm Slp S3 Min Assert</span><br><span style="color: hsl(0, 100%, 40%);">- SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpS3MinAssert;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0677 - PCH Pm Slp S4 Min Assert</span><br><span style="color: hsl(0, 100%, 40%);">- SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpS4MinAssert;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0678 - PCH Pm Slp Sus Min Assert</span><br><span style="color: hsl(0, 100%, 40%);">- SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpSusMinAssert;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0679 - PCH Pm Slp A Min Assert</span><br><span style="color: hsl(0, 100%, 40%);">- SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpAMinAssert;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x067A - SLP_S0# Override</span><br><span style="color: hsl(0, 100%, 40%);">- Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'</span><br><span style="color: hsl(0, 100%, 40%);">- will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion</span><br><span style="color: hsl(0, 100%, 40%);">- when debug is enabled. \n</span><br><span style="color: hsl(0, 100%, 40%);">- Note: This BIOS option should keep 'Auto', other options are intended for advanced</span><br><span style="color: hsl(0, 100%, 40%);">- configuration only.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disabled, 1:Enabled, 2:Auto</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SlpS0Override;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x067B - S0ix Override Settings</span><br><span style="color: hsl(0, 100%, 40%);">- Select 'Auto', it will be auto-configured according to probe type. 'No Change' will</span><br><span style="color: hsl(0, 100%, 40%);">- keep PMC default settings. Or select the desired debug probe type for S0ix Override</span><br><span style="color: hsl(0, 100%, 40%);">- settings.\n</span><br><span style="color: hsl(0, 100%, 40%);">- Reminder: DCI OOB (aka BSSB) uses CCA probe.\n</span><br><span style="color: hsl(0, 100%, 40%);">- Note: This BIOS option should keep 'Auto', other options are intended for advanced</span><br><span style="color: hsl(0, 100%, 40%);">- configuration only.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SlpS0DisQForDebug;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x067C - USB Overcurrent Override for DbC</span><br><span style="color: hsl(0, 100%, 40%);">- This option overrides USB Over Current enablement state that USB OC will be disabled</span><br><span style="color: hsl(0, 100%, 40%);">- after enabling this option. Enable when DbC is used to avoid signaling conflicts.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchEnableDbcObs;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x067D</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace20[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0680 - PCH Pm Lpc Clock Run</span><br><span style="color: hsl(0, 100%, 40%);">- This member describes whether or not the LPC ClockRun feature of PCH should be enabled.</span><br><span style="color: hsl(0, 100%, 40%);">- Default value is Disabled</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmLpcClockRun;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0681 - PCH Pm Slp Strch Sus Up</span><br><span style="color: hsl(0, 100%, 40%);">- Enable SLP_X Stretching After SUS Well Power Up.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpStrchSusUp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0682 - PCH Pm Slp Lan Low Dc</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable SLP_LAN# Low on DC Power.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpLanLowDc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0683 - PCH Pm Pwr Btn Override Period</span><br><span style="color: hsl(0, 100%, 40%);">- PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmPwrBtnOverridePeriod;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown</span><br><span style="color: hsl(0, 100%, 40%);">- When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmDisableDsxAcPresentPulldown;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0685</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace21;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0686 - PCH Pm Disable Native Power Button</span><br><span style="color: hsl(0, 100%, 40%);">- Power button native mode disable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmDisableNativePowerButton;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0687 - PCH Pm Slp S0 Enable</span><br><span style="color: hsl(0, 100%, 40%);">- Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmSlpS0Enable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0688 - PCH Pm ME_WAKE_STS</span><br><span style="color: hsl(0, 100%, 40%);">- Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmMeWakeSts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS</span><br><span style="color: hsl(0, 100%, 40%);">- Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmWolOvrWkSts;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x068A - PCH Pm Reset Power Cycle Duration</span><br><span style="color: hsl(0, 100%, 40%);">- Could be customized in the unit of second. Please refer to EDS for all support settings.</span><br><span style="color: hsl(0, 100%, 40%);">- 0 is default, 1 is 1 second, 2 is 2 seconds, ...</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmPwrCycDur;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x068B - PCH Pm Pcie Pll Ssc</span><br><span style="color: hsl(0, 100%, 40%);">- Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No</span><br><span style="color: hsl(0, 100%, 40%);">- BIOS override.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmPciePllSsc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x068C</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace22;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x068D - PCH Sata Pwr Opt Enable</span><br><span style="color: hsl(0, 100%, 40%);">- SATA Power Optimizer on PCH side.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPwrOptEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x068E - PCH Sata eSATA Speed Limit</span><br><span style="color: hsl(0, 100%, 40%);">- When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EsataSpeedLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x068F - PCH Sata Speed Limit</span><br><span style="color: hsl(0, 100%, 40%);">- Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataSpeedLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0690 - Enable SATA Port HotPlug</span><br><span style="color: hsl(0, 100%, 40%);">- Enable SATA Port HotPlug.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsHotPlug[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0698 - Enable SATA Port Interlock Sw</span><br><span style="color: hsl(0, 100%, 40%);">- Enable SATA Port Interlock Sw.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsInterlockSw[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06A0 - Enable SATA Port External</span><br><span style="color: hsl(0, 100%, 40%);">- Enable SATA Port External.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsExternal[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06A8 - Enable SATA Port SpinUp</span><br><span style="color: hsl(0, 100%, 40%);">- Enable the COMRESET initialization Sequence to the device.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsSpinUp[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06B0 - Enable SATA Port Solid State Drive</span><br><span style="color: hsl(0, 100%, 40%);">- 0: HDD; 1: SSD.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsSolidStateDrive[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06B8 - Enable SATA Port Enable Dito Config</span><br><span style="color: hsl(0, 100%, 40%);">- Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsEnableDitoConfig[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06C0 - Enable SATA Port DmVal</span><br><span style="color: hsl(0, 100%, 40%);">- DITO multiplier. Default is 15.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsDmVal[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06C8 - Enable SATA Port DmVal</span><br><span style="color: hsl(0, 100%, 40%);">- DEVSLP Idle Timeout (DITO), Default is 625.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 SataPortsDitoVal[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06D8 - Enable SATA Port ZpOdd</span><br><span style="color: hsl(0, 100%, 40%);">- Support zero power ODD.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataPortsZpOdd[8];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E0 - PCH Sata Rst Raid Device Id</span><br><span style="color: hsl(0, 100%, 40%);">- Enable RAID Alternate ID.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Client, 1:Alternate, 2:Server</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstRaidDeviceId;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E1 - PCH Sata Rst Raid0</span><br><span style="color: hsl(0, 100%, 40%);">- RAID0.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstRaid0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E2 - PCH Sata Rst Raid1</span><br><span style="color: hsl(0, 100%, 40%);">- RAID1.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstRaid1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E3 - PCH Sata Rst Raid10</span><br><span style="color: hsl(0, 100%, 40%);">- RAID10.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstRaid10;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E4 - PCH Sata Rst Raid5</span><br><span style="color: hsl(0, 100%, 40%);">- RAID5.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstRaid5;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E5 - PCH Sata Rst Irrt</span><br><span style="color: hsl(0, 100%, 40%);">- Intel Rapid Recovery Technology.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstIrrt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner</span><br><span style="color: hsl(0, 100%, 40%);">- OROM UI and BANNER.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstOromUiBanner;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay</span><br><span style="color: hsl(0, 100%, 40%);">- 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstOromUiDelay;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E8 - PCH Sata Rst Hdd Unlock</span><br><span style="color: hsl(0, 100%, 40%);">- Indicates that the HDD password unlock in the OS is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstHddUnlock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06E9 - PCH Sata Rst Led Locate</span><br><span style="color: hsl(0, 100%, 40%);">- Indicates that the LED/SGPIO hardware is attached and ping to locate feature is</span><br><span style="color: hsl(0, 100%, 40%);">- enabled on the OS.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstLedLocate;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06EA - PCH Sata Rst Irrt Only</span><br><span style="color: hsl(0, 100%, 40%);">- Allow only IRRT drives to span internal and external ports.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstIrrtOnly;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06EB - PCH Sata Rst Smart Storage</span><br><span style="color: hsl(0, 100%, 40%);">- RST Smart Storage caching Bit.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstSmartStorage;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable</span><br><span style="color: hsl(0, 100%, 40%);">- Enable Intel RST for PCIe Storage remapping.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstPcieEnable[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06EF - PCH Sata Rst Pcie Storage Port</span><br><span style="color: hsl(0, 100%, 40%);">- Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstPcieStoragePort[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay</span><br><span style="color: hsl(0, 100%, 40%);">- PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstPcieDeviceResetDelay[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06F5 - Enable eMMC HS400 Training</span><br><span style="color: hsl(0, 100%, 40%);">- Deprecated.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchScsEmmcHs400TuningRequired;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06F6 - Set HS400 Tuning Data Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Set if HS400 Tuning Data Valid.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchScsEmmcHs400DllDataValid;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06F7 - Rx Strobe Delay Control</span><br><span style="color: hsl(0, 100%, 40%);">- Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchScsEmmcHs400RxStrobeDll1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06F8 - Tx Data Delay Control</span><br><span style="color: hsl(0, 100%, 40%);">- Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchScsEmmcHs400TxDataDll;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06F9 - I/O Driver Strength</span><br><span style="color: hsl(0, 100%, 40%);">- Deprecated.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:33 Ohm, 1:40 Ohm, 2:50 Ohm</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchScsEmmcHs400DriverStrength;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x06FA - PCH SerialIo I2C Pads Termination</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5</span><br><span style="color: hsl(0, 100%, 40%);">- pads termination respectively. One byte for each controller, byte0 for I2C0, byte1</span><br><span style="color: hsl(0, 100%, 40%);">- for I2C1, and so on.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchSerialIoI2cPadsTermination[6];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0700</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace23;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0701 - PcdSerialIoUart0PinMuxing</span><br><span style="color: hsl(0, 100%, 40%);">- Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:default pins, 1:pins muxed with CNV_BRI/RGI</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SerialIoUart0PinMuxing;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0702</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace24[1];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines</span><br><span style="color: hsl(0, 100%, 40%);">- Enables UART hardware flow control, CTS and RTS linesh.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SerialIoUartHwFlowCtrl[3];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0706 - UART Number For Debug Purpose</span><br><span style="color: hsl(0, 100%, 40%);">- UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected</span><br><span style="color: hsl(0, 100%, 40%);">- as CNVi BT Core interface, it cannot be used for debug purpose.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:UART0, 1:UART1, 2:UART2</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SerialIoDebugUartNumber;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0707 - Enable Debug UART Controller</span><br><span style="color: hsl(0, 100%, 40%);">- Enable debug UART controller after post.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SerialIoEnableDebugUartAfterPost;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0708 - Enable Serial IRQ</span><br><span style="color: hsl(0, 100%, 40%);">- Determines if enable Serial IRQ.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchSirqEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0709 - Serial IRQ Mode Select</span><br><span style="color: hsl(0, 100%, 40%);">- Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchSirqMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x070A - Start Frame Pulse Width</span><br><span style="color: hsl(0, 100%, 40%);">- Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.</span><br><span style="color: hsl(0, 100%, 40%);">- 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchStartFramePulse;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x070B - Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedForFuture1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x070C - Thermal Device SMI Enable</span><br><span style="color: hsl(0, 100%, 40%);">- This locks down SMI Enable on Alert Thermal Sensor Trip.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchTsmicLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x070D - Thermal Throttling Custimized T0Level Value</span><br><span style="color: hsl(0, 100%, 40%);">- Custimized T0Level value.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PchT0Level;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x070F - Thermal Throttling Custimized T1Level Value</span><br><span style="color: hsl(0, 100%, 40%);">- Custimized T1Level value.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PchT1Level;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0711 - Thermal Throttling Custimized T2Level Value</span><br><span style="color: hsl(0, 100%, 40%);">- Custimized T2Level value.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PchT2Level;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0713 - Enable The Thermal Throttle</span><br><span style="color: hsl(0, 100%, 40%);">- Enable the thermal throttle function.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchTTEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0714 - PMSync State 13</span><br><span style="color: hsl(0, 100%, 40%);">- When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force</span><br><span style="color: hsl(0, 100%, 40%);">- at least T2 state.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchTTState13Enable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0715 - Thermal Throttle Lock</span><br><span style="color: hsl(0, 100%, 40%);">- Thermal Throttle Lock.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchTTLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0716 - Thermal Throttling Suggested Setting</span><br><span style="color: hsl(0, 100%, 40%);">- Thermal Throttling Suggested Setting.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TTSuggestedSetting;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0717 - Enable PCH Cross Throttling</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable PCH Cross Throttling</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TTCrossThrottling;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable</span><br><span style="color: hsl(0, 100%, 40%);">- DMI Thermal Sensor Autonomous Width Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchDmiTsawEn;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0719 - DMI Thermal Sensor Suggested Setting</span><br><span style="color: hsl(0, 100%, 40%);">- DMT thermal sensor suggested representative values.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DmiSuggestedSetting;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x071A - Thermal Sensor 0 Target Width</span><br><span style="color: hsl(0, 100%, 40%);">- DMT thermal sensor suggested representative values.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DmiTS0TW;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x071B - Thermal Sensor 1 Target Width</span><br><span style="color: hsl(0, 100%, 40%);">- Thermal Sensor 1 Target Width.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DmiTS1TW;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x071C - Thermal Sensor 2 Target Width</span><br><span style="color: hsl(0, 100%, 40%);">- Thermal Sensor 2 Target Width.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DmiTS2TW;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x071D - Thermal Sensor 3 Target Width</span><br><span style="color: hsl(0, 100%, 40%);">- Thermal Sensor 3 Target Width.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DmiTS3TW;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x071E - Port 0 T1 Multipler</span><br><span style="color: hsl(0, 100%, 40%);">- Port 0 T1 Multipler.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP0T1M;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x071F - Port 0 T2 Multipler</span><br><span style="color: hsl(0, 100%, 40%);">- Port 0 T2 Multipler.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP0T2M;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0720 - Port 0 T3 Multipler</span><br><span style="color: hsl(0, 100%, 40%);">- Port 0 T3 Multipler.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP0T3M;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0721 - Port 0 Tdispatch</span><br><span style="color: hsl(0, 100%, 40%);">- Port 0 Tdispatch.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP0TDisp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0722 - Port 1 T1 Multipler</span><br><span style="color: hsl(0, 100%, 40%);">- Port 1 T1 Multipler.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP1T1M;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0723 - Port 1 T2 Multipler</span><br><span style="color: hsl(0, 100%, 40%);">- Port 1 T2 Multipler.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP1T2M;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0724 - Port 1 T3 Multipler</span><br><span style="color: hsl(0, 100%, 40%);">- Port 1 T3 Multipler.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP1T3M;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0725 - Port 1 Tdispatch</span><br><span style="color: hsl(0, 100%, 40%);">- Port 1 Tdispatch.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP1TDisp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0726 - Port 0 Tinactive</span><br><span style="color: hsl(0, 100%, 40%);">- Port 0 Tinactive.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP0Tinact;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch</span><br><span style="color: hsl(0, 100%, 40%);">- Port 0 Alternate Fast Init Tdispatch.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP0TDispFinit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0728 - Port 1 Tinactive</span><br><span style="color: hsl(0, 100%, 40%);">- Port 1 Tinactive.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP1Tinact;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch</span><br><span style="color: hsl(0, 100%, 40%);">- Port 1 Alternate Fast Init Tdispatch.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataP1TDispFinit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x072A - Sata Thermal Throttling Suggested Setting</span><br><span style="color: hsl(0, 100%, 40%);">- Sata Thermal Throttling Suggested Setting.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataThermalSuggestedSetting;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x072B - Enable Memory Thermal Throttling</span><br><span style="color: hsl(0, 100%, 40%);">- Enable Memory Thermal Throttling.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchMemoryThrottlingEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x072C - Memory Thermal Throttling</span><br><span style="color: hsl(0, 100%, 40%);">- Enable Memory Thermal Throttling.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchMemoryPmsyncEnable[2];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x072E - Enable Memory Thermal Throttling</span><br><span style="color: hsl(0, 100%, 40%);">- Enable Memory Thermal Throttling.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchMemoryC0TransmitEnable[2];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0730 - Enable Memory Thermal Throttling</span><br><span style="color: hsl(0, 100%, 40%);">- Enable Memory Thermal Throttling.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchMemoryPinSelection[2];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0732 - Thermal Device Temperature</span><br><span style="color: hsl(0, 100%, 40%);">- Decides the temperature.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PchTemperatureHotLevel;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0734 - Enable xHCI Compliance Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Compliance Mode can be enabled for testing through this option but this is disabled</span><br><span style="color: hsl(0, 100%, 40%);">- by default.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchEnableComplianceMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0735 - USB2 Port Over Current Pin</span><br><span style="color: hsl(0, 100%, 40%);">- Describe the specific over current pin number of USB 2.0 Port N.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb2OverCurrentPin[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0745 - USB3 Port Over Current Pin</span><br><span style="color: hsl(0, 100%, 40%);">- Describe the specific over current pin number of USB 3.0 Port N.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Usb3OverCurrentPin[10];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x074F - Enable 8254 Static Clock Gating</span><br><span style="color: hsl(0, 100%, 40%);">- Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time</span><br><span style="color: hsl(0, 100%, 40%);">- might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support</span><br><span style="color: hsl(0, 100%, 40%);">- boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Enable8254ClockGating;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0750 - PCH Sata Rst Optane Memory</span><br><span style="color: hsl(0, 100%, 40%);">- Optane Memory</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstOptaneMemory;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0751 - PCH Sata Rst CPU Attached Storage</span><br><span style="color: hsl(0, 100%, 40%);">- CPU Attached Storage</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstCpuAttachedStorage;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0752</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace25[2];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0754 - Pch PCIE device override table pointer</span><br><span style="color: hsl(0, 100%, 40%);">- The PCIe device table is being used to override PCIe device ASPM settings. This</span><br><span style="color: hsl(0, 100%, 40%);">- is a pointer points to a 32bit address. And it's only used in PostMem phase. Please</span><br><span style="color: hsl(0, 100%, 40%);">- refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId</span><br><span style="color: hsl(0, 100%, 40%);">- must be 0.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PchPcieDeviceOverrideTablePtr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0758 - Enable TCO timer.</span><br><span style="color: hsl(0, 100%, 40%);">- When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have</span><br><span style="color: hsl(0, 100%, 40%);">- huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer</span><br><span style="color: hsl(0, 100%, 40%);">- emulation must be enabled, and WDAT table must not be exposed to the OS.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EnableTcoTimer;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0759 - BgpdtHash[4]</span><br><span style="color: hsl(0, 100%, 40%);">- BgpdtHash values</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 BgpdtHash[4];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0779 - BiosGuardAttr</span><br><span style="color: hsl(0, 100%, 40%);">- BiosGuardAttr default values</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 BiosGuardAttr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x077D - BiosGuardModulePtr</span><br><span style="color: hsl(0, 100%, 40%);">- BiosGuardModulePtr default values</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 BiosGuardModulePtr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0785 - SendEcCmd</span><br><span style="color: hsl(0, 100%, 40%);">- SendEcCmd function pointer. \n</span><br><span style="color: hsl(0, 100%, 40%);">- @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE</span><br><span style="color: hsl(0, 100%, 40%);">- EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 SendEcCmd;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x078D - EcCmdProvisionEav</span><br><span style="color: hsl(0, 100%, 40%);">- Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EcCmdProvisionEav;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x078E - EcCmdLock</span><br><span style="color: hsl(0, 100%, 40%);">- EcCmdLock default values. Locks Ephemeral Authorization Value sent previously</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EcCmdLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x078F - SgxEpoch0</span><br><span style="color: hsl(0, 100%, 40%);">- SgxEpoch0 default values</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 SgxEpoch0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0797 - SgxEpoch1</span><br><span style="color: hsl(0, 100%, 40%);">- SgxEpoch1 default values</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 SgxEpoch1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x079F - SgxSinitNvsData</span><br><span style="color: hsl(0, 100%, 40%);">- SgxSinitNvsData default values</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SgxSinitNvsData;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07A0 - Si Config CSM Flag.</span><br><span style="color: hsl(0, 100%, 40%);">- Platform specific common policies that used by several silicon components. CSM status flag.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SiCsmFlag;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07A1</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 SiSsidTablePtr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07A5</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 SiNumberOfSsidTableEntry;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07A7 - SATA RST Interrupt Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Msix, 1:Msi, 2:Legacy</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataRstInterrupt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07A8 - ME Unconfig on RTC clear</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- 2: Cmos is clear, status unkonwn. 3: Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos</span><br><span style="color: hsl(0, 100%, 40%);">- is clear, 3: Reserved</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MeUnconfigOnRtcClear;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07A9 - Enable PS_ON.</span><br><span style="color: hsl(0, 100%, 40%);">- PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power</span><br><span style="color: hsl(0, 100%, 40%);">- target that will be required by the California Energy Commission (CEC). When FALSE,</span><br><span style="color: hsl(0, 100%, 40%);">- PS_ON is to be disabled.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PsOnEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO</span><br><span style="color: hsl(0, 100%, 40%);">- and VccSTG rails instead of SLP_S0# pin.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PmcCpuC10GatePinEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07AB - Pch Dmi Aspm Ctrl</span><br><span style="color: hsl(0, 100%, 40%);">- ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b></span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchDmiAspmCtrl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07AC</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsUpd[1];</span><br><span style="color: hsl(0, 100%, 40%);">-} FSP_S_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Fsp S Test Configuration</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07AD</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Signature;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07B1 - Enable/Disable Device 7</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: Device 7 enabled, Disable (Default): Device 7 disabled</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ChapDeviceEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07B2 - Skip PAM register lock</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):</span><br><span style="color: hsl(0, 100%, 40%);">- PAM registers will be locked by RC</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SkipPamLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07B3 - EDRAM Test Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):</span><br><span style="color: hsl(0, 100%, 40%);">- PAM registers will be locked by RC</span><br><span style="color: hsl(0, 100%, 40%);">- 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EdramTestMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07B4 - DMI Extended Sync Control</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended</span><br><span style="color: hsl(0, 100%, 40%);">- Sync Control</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DmiExtSync;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07B5 - DMI IOT Control</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DmiIot;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07B6 - PEG Max Payload size per root port</span><br><span style="color: hsl(0, 100%, 40%);">- 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B</span><br><span style="color: hsl(0, 100%, 40%);">- 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PegMaxPayload[4];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07BA - Enable/Disable IGFX RenderStandby</span><br><span style="color: hsl(0, 100%, 40%);">- Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 RenderStandby;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07BB - Enable/Disable IGFX PmSupport</span><br><span style="color: hsl(0, 100%, 40%);">- Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PmSupport;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07BC - Enable/Disable CdynmaxClamp</span><br><span style="color: hsl(0, 100%, 40%);">- Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CdynmaxClampEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07BD - Disable VT-d</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 VtdDisable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07BE - GT Frequency Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,</span><br><span style="color: hsl(0, 100%, 40%);">- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:</span><br><span style="color: hsl(0, 100%, 40%);">- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x18: 1200 Mhz</span><br><span style="color: hsl(0, 100%, 40%);">- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,</span><br><span style="color: hsl(0, 100%, 40%);">- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:</span><br><span style="color: hsl(0, 100%, 40%);">- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x18: 1200 Mhz</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 GtFreqMax;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07BF - Disable Turbo GT</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DisableTurboGt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07C0 - SaPostMemTestRsvd</span><br><span style="color: hsl(0, 100%, 40%);">- Reserved for SA Post-Mem Test</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SaPostMemTestRsvd[11];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07CB - 1-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit,</span><br><span style="color: hsl(0, 100%, 40%);">- 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 OneCoreRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07CC - 2-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TwoCoreRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07CD - 3-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ThreeCoreRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07CE - 4-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 FourCoreRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07CF - Enable or Disable HWP</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b></span><br><span style="color: hsl(0, 100%, 40%);">- 2-3:Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Hwp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D0 - Hardware Duty Cycle Control</span><br><span style="color: hsl(0, 100%, 40%);">- Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 HdcControl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D1 - Package Long duration turbo mode time</span><br><span style="color: hsl(0, 100%, 40%);">- Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)</span><br><span style="color: hsl(0, 100%, 40%);">- 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PowerLimit1Time;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D2 - Short Duration Turbo Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PowerLimit2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D3 - Turbo settings Lock</span><br><span style="color: hsl(0, 100%, 40%);">- Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TurboPowerLimitLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D4 - Package PL3 time window</span><br><span style="color: hsl(0, 100%, 40%);">- Package PL3 time window range for this policy from 0 to 64ms</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PowerLimit3Time;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D5 - Package PL3 Duty Cycle</span><br><span style="color: hsl(0, 100%, 40%);">- Package PL3 Duty Cycle; Valid Range is 0 to 100</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PowerLimit3DutyCycle;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D6 - Package PL3 Lock</span><br><span style="color: hsl(0, 100%, 40%);">- Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PowerLimit3Lock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D7 - Package PL4 Lock</span><br><span style="color: hsl(0, 100%, 40%);">- Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PowerLimit4Lock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D8 - TCC Activation Offset</span><br><span style="color: hsl(0, 100%, 40%);">- TCC Activation Offset. Offset from factory set TCC activation temperature at which</span><br><span style="color: hsl(0, 100%, 40%);">- the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation</span><br><span style="color: hsl(0, 100%, 40%);">- Temperature, in volts.For Y SKU, the recommended default for this policy is <b>10</b>,</span><br><span style="color: hsl(0, 100%, 40%);">- For all other SKUs the recommended default are <b>0</b></span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TccActivationOffset;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable</span><br><span style="color: hsl(0, 100%, 40%);">- Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle</span><br><span style="color: hsl(0, 100%, 40%);">- below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,</span><br><span style="color: hsl(0, 100%, 40%);">- For all other SKUs the recommended default are <b>0: Disabled</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TccOffsetClamp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07DA - Tcc Offset Lock</span><br><span style="color: hsl(0, 100%, 40%);">- Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature</span><br><span style="color: hsl(0, 100%, 40%);">- target; 0: Disabled; <b>1: Enabled </b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TccOffsetLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07DB - Custom Ratio State Entries</span><br><span style="color: hsl(0, 100%, 40%);">- The number of custom ratio state entries, ranges from 0 to 40 for a valid custom</span><br><span style="color: hsl(0, 100%, 40%);">- ratio table.Sets the number of custom P-states. At least 2 states must be present</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 NumberOfEntries;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07DC - Custom Short term Power Limit time window</span><br><span style="color: hsl(0, 100%, 40%);">- Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom1PowerLimit1Time;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07DD - Custom Turbo Activation Ratio</span><br><span style="color: hsl(0, 100%, 40%);">- Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom1TurboActivationRatio;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07DE - Custom Config Tdp Control</span><br><span style="color: hsl(0, 100%, 40%);">- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom1ConfigTdpControl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07DF - Custom Short term Power Limit time window</span><br><span style="color: hsl(0, 100%, 40%);">- Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom2PowerLimit1Time;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E0 - Custom Turbo Activation Ratio</span><br><span style="color: hsl(0, 100%, 40%);">- Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom2TurboActivationRatio;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E1 - Custom Config Tdp Control</span><br><span style="color: hsl(0, 100%, 40%);">- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom2ConfigTdpControl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E2 - Custom Short term Power Limit time window</span><br><span style="color: hsl(0, 100%, 40%);">- Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom3PowerLimit1Time;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E3 - Custom Turbo Activation Ratio</span><br><span style="color: hsl(0, 100%, 40%);">- Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom3TurboActivationRatio;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E4 - Custom Config Tdp Control</span><br><span style="color: hsl(0, 100%, 40%);">- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Custom3ConfigTdpControl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E5 - ConfigTdp mode settings Lock</span><br><span style="color: hsl(0, 100%, 40%);">- Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ConfigTdpLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E6 - Load Configurable TDP SSDT</span><br><span style="color: hsl(0, 100%, 40%);">- Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ConfigTdpBios;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E7 - PL1 Enable value</span><br><span style="color: hsl(0, 100%, 40%);">- PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PsysPowerLimit1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E8 - PL1 timewindow</span><br><span style="color: hsl(0, 100%, 40%);">- PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16</span><br><span style="color: hsl(0, 100%, 40%);">- , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PsysPowerLimit1Time;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07E9 - PL2 Enable Value</span><br><span style="color: hsl(0, 100%, 40%);">- PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;</span><br><span style="color: hsl(0, 100%, 40%);">- 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PsysPowerLimit2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MlcStreamerPrefetcher;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MlcSpatialPrefetcher;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MonitorMwaitEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07ED - Enable or Disable initialization of machine check registers</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MachineCheckEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07EE - Enable or Disable processor debug features</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DebugInterfaceEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07EF - Lock or Unlock debug interface features</span><br><span style="color: hsl(0, 100%, 40%);">- Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DebugInterfaceLockEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07F0 - AP Idle Manner of waiting for SIPI</span><br><span style="color: hsl(0, 100%, 40%);">- AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.</span><br><span style="color: hsl(0, 100%, 40%);">- 1: HALT loop, 2: MWAIT loop, 3: RUN loop</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ApIdleManner;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07F1 - Control on Processor Trace output scheme</span><br><span style="color: hsl(0, 100%, 40%);">- Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.</span><br><span style="color: hsl(0, 100%, 40%);">- 0: Single Range Output, 1: ToPA Output</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ProcessorTraceOutputScheme;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07F2 - Enable or Disable Processor Trace feature</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ProcessorTraceEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07F3 - Base of memory region allocated for Processor Trace</span><br><span style="color: hsl(0, 100%, 40%);">- Base address of memory region allocated for Processor Trace. Processor Trace requires</span><br><span style="color: hsl(0, 100%, 40%);">- 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b></span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 ProcessorTraceMemBase;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07FB - Memory region allocation for Processor Trace</span><br><span style="color: hsl(0, 100%, 40%);">- Length in bytes of memory region allocated for Processor Trace. Processor Trace</span><br><span style="color: hsl(0, 100%, 40%);">- requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b></span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 ProcessorTraceMemLength;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07FF - Enable or Disable Voltage Optimization feature</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 VoltageOptimization;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Eist;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0801 - Enable or Disable Energy Efficient P-state</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;</span><br><span style="color: hsl(0, 100%, 40%);">- <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EnergyEfficientPState;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0802 - Enable or Disable Energy Efficient Turbo</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;</span><br><span style="color: hsl(0, 100%, 40%);">- <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EnergyEfficientTurbo;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0803 - Enable or Disable T states</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable T states; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TStates;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT#</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 BiProcHot;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DisableProcHotOut;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0806 - Enable or Disable PROCHOT# Response</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ProcHotResponse;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0807 - Enable or Disable VR Thermal Alert</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DisableVrThermalAlert;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0808 - Enable or Disable Thermal Reporting</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 AutoThermalReporting;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0809 - Enable or Disable Thermal Monitor</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ThermalMonitor;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x080A - Enable or Disable CPU power states (C-states)</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Cx;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x080B - Configure C-State Configuration Lock</span><br><span style="color: hsl(0, 100%, 40%);">- Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PmgCstCfgCtrlLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x080C - Enable or Disable Enhanced C-states</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 C1e;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x080D - Enable or Disable Package Cstate Demotion</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PkgCStateDemotion;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x080E - Enable or Disable Package Cstate UnDemotion</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PkgCStateUnDemotion;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x080F - Enable or Disable CState-Pre wake</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CStatePreWake;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0810 - Enable or Disable TimedMwait Support.</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TimedMwait;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0811 - Enable or Disable IO to MWAIT redirection</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CstCfgCtrIoMwaitRedirection;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0812 - Set the Max Pkg Cstate</span><br><span style="color: hsl(0, 100%, 40%);">- Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep</span><br><span style="color: hsl(0, 100%, 40%);">- C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,</span><br><span style="color: hsl(0, 100%, 40%);">- 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PkgCStateLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0813 - TimeUnit for C-State Latency Control0</span><br><span style="color: hsl(0, 100%, 40%);">- TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(0, 100%, 40%);">- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CstateLatencyControl0TimeUnit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0814 - TimeUnit for C-State Latency Control1</span><br><span style="color: hsl(0, 100%, 40%);">- TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(0, 100%, 40%);">- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CstateLatencyControl1TimeUnit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0815 - TimeUnit for C-State Latency Control2</span><br><span style="color: hsl(0, 100%, 40%);">- TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(0, 100%, 40%);">- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CstateLatencyControl2TimeUnit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0816 - TimeUnit for C-State Latency Control3</span><br><span style="color: hsl(0, 100%, 40%);">- TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(0, 100%, 40%);">- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CstateLatencyControl3TimeUnit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0817 - TimeUnit for C-State Latency Control4</span><br><span style="color: hsl(0, 100%, 40%);">- Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CstateLatencyControl4TimeUnit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0818 - TimeUnit for C-State Latency Control5</span><br><span style="color: hsl(0, 100%, 40%);">- TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(0, 100%, 40%);">- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CstateLatencyControl5TimeUnit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0819 - Interrupt Redirection Mode Select</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:</span><br><span style="color: hsl(0, 100%, 40%);">- PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PpmIrmSetting;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x081A - Lock prochot configuration</span><br><span style="color: hsl(0, 100%, 40%);">- Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ProcHotLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x081B - Configuration for boot TDP selection</span><br><span style="color: hsl(0, 100%, 40%);">- Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP</span><br><span style="color: hsl(0, 100%, 40%);">- Up;0xFF : Deactivate</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ConfigTdpLevel;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x081C - Race To Halt</span><br><span style="color: hsl(0, 100%, 40%);">- Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency</span><br><span style="color: hsl(0, 100%, 40%);">- in order to enter pkg C-State faster to reduce overall power. (RTH is controlled</span><br><span style="color: hsl(0, 100%, 40%);">- through MSR 1FC bit 20)Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 RaceToHalt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x081D - Max P-State Ratio</span><br><span style="color: hsl(0, 100%, 40%);">- Max P-State Ratio, Valid Range 0 to 0x7F</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MaxRatio;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x081E - P-state ratios for custom P-state table</span><br><span style="color: hsl(0, 100%, 40%);">- P-state ratios for custom P-state table. NumberOfEntries has valid range between</span><br><span style="color: hsl(0, 100%, 40%);">- 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]</span><br><span style="color: hsl(0, 100%, 40%);">- are configurable. Valid Range of each entry is 0 to 0x7F</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 StateRatio[40];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table</span><br><span style="color: hsl(0, 100%, 40%);">- P-state ratios for max 16 version of custom P-state table. This table is used for</span><br><span style="color: hsl(0, 100%, 40%);">- OS versions limited to a max of 16 P-States. If the first entry of this table is</span><br><span style="color: hsl(0, 100%, 40%);">- 0, or if Number of Entries is 16 or less, then this table will be ignored, and</span><br><span style="color: hsl(0, 100%, 40%);">- up to the top 16 values of the StateRatio table will be used instead. Valid Range</span><br><span style="color: hsl(0, 100%, 40%);">- of each entry is 0 to 0x7F</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 StateRatioMax16[16];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0856 - Platform Power Pmax</span><br><span style="color: hsl(0, 100%, 40%);">- PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0-1024 Watts. Value of 800 = 100W</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PsysPmax;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 CstateLatencyControl0Irtl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 CstateLatencyControl1Irtl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 CstateLatencyControl2Irtl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 CstateLatencyControl3Irtl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 CstateLatencyControl4Irtl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 CstateLatencyControl5Irtl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0864 - Package Long duration turbo mode power limit</span><br><span style="color: hsl(0, 100%, 40%);">- Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.</span><br><span style="color: hsl(0, 100%, 40%);">- Valid Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PowerLimit1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0868 - Package Short duration turbo mode power limit</span><br><span style="color: hsl(0, 100%, 40%);">- Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PowerLimit2Power;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x086C - Package PL3 power limit</span><br><span style="color: hsl(0, 100%, 40%);">- Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PowerLimit3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0870 - Package PL4 power limit</span><br><span style="color: hsl(0, 100%, 40%);">- Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PowerLimit4;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0874 - Tcc Offset Time Window for RATL</span><br><span style="color: hsl(0, 100%, 40%);">- Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 TccOffsetTimeWindowForRatl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1</span><br><span style="color: hsl(0, 100%, 40%);">- Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Custom1PowerLimit1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x087C - Long term Power Limit value for custom cTDP level 1</span><br><span style="color: hsl(0, 100%, 40%);">- Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Custom1PowerLimit2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2</span><br><span style="color: hsl(0, 100%, 40%);">- Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Custom2PowerLimit1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2</span><br><span style="color: hsl(0, 100%, 40%);">- Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Custom2PowerLimit2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3</span><br><span style="color: hsl(0, 100%, 40%);">- Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Custom3PowerLimit1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x088C - Long term Power Limit value for custom cTDP level 3</span><br><span style="color: hsl(0, 100%, 40%);">- Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Custom3PowerLimit2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0890 - Platform PL1 power</span><br><span style="color: hsl(0, 100%, 40%);">- Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range</span><br><span style="color: hsl(0, 100%, 40%);">- 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PsysPowerLimit1Power;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0894 - Platform PL2 power</span><br><span style="color: hsl(0, 100%, 40%);">- Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range</span><br><span style="color: hsl(0, 100%, 40%);">- 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PsysPowerLimit2Power;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0898 - Set Three Strike Counter Disable</span><br><span style="color: hsl(0, 100%, 40%);">- False (default): Three Strike counter will be incremented and True: Prevents Three</span><br><span style="color: hsl(0, 100%, 40%);">- Strike counter from incrementing; <b>0: False</b>; 1: True.</span><br><span style="color: hsl(0, 100%, 40%);">- 0: False, 1: True</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ThreeStrikeCounterDisable;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT</span><br><span style="color: hsl(0, 100%, 40%);">- Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 HwpInterruptControl;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x089A - 5-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0:0xFF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 FiveCoreRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x089B - 6-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0:0xFF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SixCoreRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x089C - 7-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0:0xFF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SevenCoreRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x089D - 8-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0:0xFF</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EightCoreRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x089E - Intel Turbo Boost Max Technology 3.0</span><br><span style="color: hsl(0, 100%, 40%);">- Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EnableItbm;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver</span><br><span style="color: hsl(0, 100%, 40%);">- Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EnableItbmDriver;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 C1StateAutoDemotion;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 C1StateUnDemotion;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A2 - CpuWakeUpTimer</span><br><span style="color: hsl(0, 100%, 40%);">- Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased</span><br><span style="color: hsl(0, 100%, 40%);">- to 180 seconds. 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 CpuWakeUpTimer;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A3 - Minimum Ring ratio limit override</span><br><span style="color: hsl(0, 100%, 40%);">- Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo</span><br><span style="color: hsl(0, 100%, 40%);">- ratio limit</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MinRingRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A4 - Minimum Ring ratio limit override</span><br><span style="color: hsl(0, 100%, 40%);">- Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo</span><br><span style="color: hsl(0, 100%, 40%);">- ratio limit</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MaxRingRatioLimit;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 C3StateAutoDemotion;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion</span><br><span style="color: hsl(0, 100%, 40%);">- Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 C3StateUnDemotion;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A7 - ReservedCpuPostMemTest</span><br><span style="color: hsl(0, 100%, 40%);">- Reserved for CPU Post-Mem Test</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedCpuPostMemTest[19];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08BA - SgxSinitDataFromTpm</span><br><span style="color: hsl(0, 100%, 40%);">- SgxSinitDataFromTpm default values</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SgxSinitDataFromTpm;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08BB - End of Post message</span><br><span style="color: hsl(0, 100%, 40%);">- Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):</span><br><span style="color: hsl(0, 100%, 40%);">- EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 EndOfPostMessage;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08BC - D0I3 Setting for HECI Disable</span><br><span style="color: hsl(0, 100%, 40%);">- Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all</span><br><span style="color: hsl(0, 100%, 40%);">- HECI devices</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DisableD0I3SettingForHeci;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08BD - HD Audio Reset Wait Timer</span><br><span style="color: hsl(0, 100%, 40%);">- The delay timer after Azalia reset, the value is number of microseconds. Default is 600.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PchHdaResetWaitTimer;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08BF - Enable LOCKDOWN SMI</span><br><span style="color: hsl(0, 100%, 40%);">- Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchLockDownGlobalSmi;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface</span><br><span style="color: hsl(0, 100%, 40%);">- Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchLockDownBiosInterface;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08C1 - Unlock all GPIO pads</span><br><span style="color: hsl(0, 100%, 40%);">- Force all GPIO pads to be unlocked for debug purpose.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchUnlockGpioPads;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08C2 - PCH Unlock SBI access</span><br><span style="color: hsl(0, 100%, 40%);">- Deprecated</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchSbiUnlock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08C3 - PCH Unlock SideBand access</span><br><span style="color: hsl(0, 100%, 40%);">- The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before</span><br><span style="color: hsl(0, 100%, 40%);">- 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchSbAccessUnlock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting, Max Snoop Latency.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PcieRpLtrMaxSnoopLatency[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting, Max Non-Snoop Latency.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PcieRpLtrMaxNoSnoopLatency[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0924 - PCIE RP Snoop Latency Override Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting, Snoop Latency Override Mode.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpSnoopLatencyOverrideMode[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting, Snoop Latency Override Multiplier.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0954 - PCIE RP Snoop Latency Override Value</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting, Snoop Latency Override Value.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PcieRpSnoopLatencyOverrideValue[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting, Non-Snoop Latency Override Mode.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpNonSnoopLatencyOverrideMode[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value</span><br><span style="color: hsl(0, 100%, 40%);">- Latency Tolerance Reporting, Non-Snoop Latency Override Value.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PcieRpNonSnoopLatencyOverrideValue[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x09E4 - PCIE RP Slot Power Limit Scale</span><br><span style="color: hsl(0, 100%, 40%);">- Specifies scale used for slot power limit value. Leave as 0 to set to default.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpSlotPowerLimitScale[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x09FC - PCIE RP Slot Power Limit Value</span><br><span style="color: hsl(0, 100%, 40%);">- Specifies upper limit on power supplie by slot. Leave as 0 to set to default.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PcieRpSlotPowerLimitValue[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset</span><br><span style="color: hsl(0, 100%, 40%);">- Used during Gen3 Link Equalization. Used for all lanes. Default is 5.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpUptp[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset</span><br><span style="color: hsl(0, 100%, 40%);">- Used during Gen3 Link Equalization. Used for all lanes. Default is 7.</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieRpDptp[24];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A5C - PCIE RP Enable Port8xh Decode</span><br><span style="color: hsl(0, 100%, 40%);">- This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;</span><br><span style="color: hsl(0, 100%, 40%);">- 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PcieEnablePort8xhDecode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A5D - PCIE Port8xh Decode Port Index</span><br><span style="color: hsl(0, 100%, 40%);">- The Index of PCIe Port that is selected for Port8xh Decode (0 Based).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPciePort8xhDecodePortIndex;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A5E - PCH Energy Reporting</span><br><span style="color: hsl(0, 100%, 40%);">- Disable/Enable PCH to CPU energy report feature.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchPmDisableEnergyReport;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A5F - PCH Sata Test Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Allow entrance to the PCH SATA test modes.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SataTestMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable</span><br><span style="color: hsl(0, 100%, 40%);">- If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning</span><br><span style="color: hsl(0, 100%, 40%);">- that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PchXhciOcLock;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A61</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace26[17];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A72 - Skip POSTBOOT SAI</span><br><span style="color: hsl(0, 100%, 40%);">- Deprecated</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SkipPostBootSai;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A73 - Mctp Broadcast Cycle</span><br><span style="color: hsl(0, 100%, 40%);">- Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MctpBroadcastCycle;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A74</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsTestUpd[12];</span><br><span style="color: hsl(0, 100%, 40%);">-} FSP_S_TEST_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Fsp S UPD Configuration</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0000</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_UPD_HEADER FspUpdHeader;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0020</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_S_CONFIG FspsConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x07AD</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_S_TEST_CONFIG FspsTestConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0A80</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 UpdTerminator;</span><br><span style="color: hsl(0, 100%, 40%);">-} FSPS_UPD;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#pragma pack()</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S Configuration
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020 - Logo Pointer
</span><br><span style="color: hsl(120, 100%, 40%);">+ Points to PEI Display Logo Image
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 LogoPtr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0024 - Logo Size
</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of PEI Display Logo Image
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 LogoSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0028 - Graphics Configuration Ptr
</span><br><span style="color: hsl(120, 100%, 40%);">+ Points to VBT
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GraphicsConfigPtr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x002C - Enable Device 4
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Device 4
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Device4Enable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x002D - Enable HD Audio DSP
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio DSP feature.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaDspEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x002E
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace0[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0031 - Enable eMMC Controller
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable eMMC Controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScsEmmcEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0032 - Enable eMMC HS400 Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable eMMC HS400 Mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScsEmmcHs400Enabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0033 - Enable SdCard Controller
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SD Card Controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScsSdCardEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0034 - Show SPI controller
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable to show SPI controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ShowSpiController;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0035
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0038 - MicrocodeRegionBase
</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory Base of Microcode Updates
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MicrocodeRegionBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x003C - MicrocodeRegionSize
</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of Microcode Updates
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MicrocodeRegionSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040 - Turbo Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable Turbo mode. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TurboMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0041 - Enable SATA SALP Support
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SATA Aggressive Link Power Management.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataSalpSupport;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0042 - Enable SATA ports
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
</span><br><span style="color: hsl(120, 100%, 40%);">+ and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsEnable[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x004A - Enable SATA DEVSLP Feature
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
</span><br><span style="color: hsl(120, 100%, 40%);">+ port, byte0 for port0, byte1 for port1, and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsDevSlp[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0052 - Enable USB2 ports
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
</span><br><span style="color: hsl(120, 100%, 40%);">+ port1, and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PortUsb20Enable[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0062 - Enable USB3 ports
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
</span><br><span style="color: hsl(120, 100%, 40%);">+ port1, and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PortUsb30Enable[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x006C - Enable xDCI controller
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable to xDCI controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 XdciEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x006D
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace2[2];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x006F - Enable SerialIo Device Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable
</span><br><span style="color: hsl(120, 100%, 40%);">+ SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device
</span><br><span style="color: hsl(120, 100%, 40%);">+ mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1,
</span><br><span style="color: hsl(120, 100%, 40%);">+ and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoDevMode[12];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
</span><br><span style="color: hsl(120, 100%, 40%);">+ The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 DevIntConfigPtr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x007F - Number of DevIntConfig Entry
</span><br><span style="color: hsl(120, 100%, 40%);">+ Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
</span><br><span style="color: hsl(120, 100%, 40%);">+ must not be NULL.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 NumOfDevIntConfig;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0080 - PIRQx to IRQx Map Config
</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
</span><br><span style="color: hsl(120, 100%, 40%);">+ 8259 PCI mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PxRcConfig[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0088 - Select GPIO IRQ Route
</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO IRQ Select. The valid value is 14 or 15.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GpioIrqRoute;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0089 - Select SciIrqSelect
</span><br><span style="color: hsl(120, 100%, 40%);">+ SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SciIrqSelect;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x008A - Select TcoIrqSelect
</span><br><span style="color: hsl(120, 100%, 40%);">+ TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TcoIrqSelect;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x008B - Enable/Disable Tco IRQ
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable TCO IRQ
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TcoIrqEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x008C - PCH HDA Verb Table Entry Number
</span><br><span style="color: hsl(120, 100%, 40%);">+ Number of Entries in Verb Table.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaVerbTableEntryNum;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x008D - PCH HDA Verb Table Pointer
</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer to Array of pointers to Verb Table.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PchHdaVerbTablePtr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0091 - PCH HDA Codec Sx Wake Capability
</span><br><span style="color: hsl(120, 100%, 40%);">+ Capability to detect wake initiated by a codec in Sx
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaCodecSxWakeCapability;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0092 - Enable SATA
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SATA controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0093 - SATA Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SATA controller working mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:AHCI, 1:RAID
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0094 - USB Per Port HS Preemphasis Bias
</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePetxiset[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A4 - USB Per Port HS Transmitter Bias
</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfeTxiset[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis
</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePredeemp[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis
</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
</span><br><span style="color: hsl(120, 100%, 40%);">+ One byte for each port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePehalfbit[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
</span><br><span style="color: hsl(120, 100%, 40%);">+ in arrary can be between 0-1. One byte for each port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3HsioTxDeEmphEnable[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
</span><br><span style="color: hsl(120, 100%, 40%);">+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3HsioTxDeEmph[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
</span><br><span style="color: hsl(120, 100%, 40%);">+ in arrary can be between 0-1. One byte for each port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3HsioTxDownscaleAmpEnable[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment
</span><br><span style="color: hsl(120, 100%, 40%);">+ USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
</span><br><span style="color: hsl(120, 100%, 40%);">+ = 00h</b>. One byte for each port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3HsioTxDownscaleAmp[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FC - Enable LAN
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable LAN controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLanEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FD - Enable HD Audio Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkHda;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FE - Enable HD Audio DMIC0 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkDmic0;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FF - Enable HD Audio DMIC1 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkDmic1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0100 - Enable HD Audio SSP0 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSsp0;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0101 - Enable HD Audio SSP1 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSsp1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0102 - Enable HD Audio SSP2 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SSP2/I2S link.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSsp2;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0103 - Enable HD Audio SoundWire#1 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SNDW1 link. Muxed with HDA.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSndw1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0104 - Enable HD Audio SoundWire#2 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSndw2;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0105 - Enable HD Audio SoundWire#3 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSndw3;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0106 - Enable HD Audio SoundWire#4 Link
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSndw4;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaSndwBufferRcomp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0108 - PTM for PCIE RP Mask
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ One bit for each port, bit0 for port1, bit1 for port2, and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcieRpPtmMask;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x010C - DPC for PCIE RP Mask
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ One bit for each port, bit0 for port1, bit1 for port2, and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcieRpDpcMask;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0110 - DPC Extensions PCIE RP Mask
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
</span><br><span style="color: hsl(120, 100%, 40%);">+ for each port, bit0 for port1, bit1 for port2, and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcieRpDpcExtensionsMask;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0114 - USB PDO Programming
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
</span><br><span style="color: hsl(120, 100%, 40%);">+ during later phase. 1: enable, 0: disable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UsbPdoProgramming;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0115 - Power button debounce configuration
</span><br><span style="color: hsl(120, 100%, 40%);">+ Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
</span><br><span style="color: hsl(120, 100%, 40%);">+ be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PmcPowerButtonDebounce;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0119 - PCH eSPI Master and Slave BME enabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH eSPI Master and Slave BME enabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchEspiBmeMasterSlaveEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011A - PCH SATA use RST Legacy OROM
</span><br><span style="color: hsl(120, 100%, 40%);">+ Use PCH SATA RST Legacy OROM when CSM is Enabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstLegacyOrom;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011B - Trace Hub Memory Base
</span><br><span style="color: hsl(120, 100%, 40%);">+ If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
</span><br><span style="color: hsl(120, 100%, 40%);">+ trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
</span><br><span style="color: hsl(120, 100%, 40%);">+ memory is configured properly.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TraceHubMemBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011F - PMC Debug Message Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
</span><br><span style="color: hsl(120, 100%, 40%);">+ will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmcDbgMsgEn;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0120 - Pointer of ChipsetInit Binary
</span><br><span style="color: hsl(120, 100%, 40%);">+ ChipsetInit Binary Pointer.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 ChipsetInitBinPtr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0124 - Length of ChipsetInit Binary
</span><br><span style="color: hsl(120, 100%, 40%);">+ ChipsetInit Binary Length.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 ChipsetInitBinLen;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0128 - PchPostMemRsvd
</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for PCH Post-Mem
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPostMemRsvd[29];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0145 - Enable Ufs Controller
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Ufs 2.0 Controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScsUfsEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0146 - CNVi Configuration
</span><br><span style="color: hsl(120, 100%, 40%);">+ This option allows for automatic detection of Connectivity Solution. [Auto Detection]
</span><br><span style="color: hsl(120, 100%, 40%);">+ assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Auto
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchCnviMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0147 - SdCard power enable polarity
</span><br><span style="color: hsl(120, 100%, 40%);">+ Choose SD_PWREN# polarity
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Active low, 1: Active high
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SdCardPowerEnableActiveHigh;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0148 - PCH USB2 PHY Power Gating enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
</span><br><span style="color: hsl(120, 100%, 40%);">+ Sus Well PG
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUsb2PhySusPgEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0149 - PCH USB OverCurrent mapping enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
</span><br><span style="color: hsl(120, 100%, 40%);">+ mapping allow for NOA usage of OC pins
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUsbOverCurrentEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014A
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace3;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014B - CNVi MfUart1 Type
</span><br><span style="color: hsl(120, 100%, 40%);">+ This option configures Uart type which connects to MfUart1
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchCnviMfUart1Type;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014C - Espi Lgmr Memory Range decode
</span><br><span style="color: hsl(120, 100%, 40%);">+ This option enables or disables espi lgmr
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchEspiLgmrEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014D - HECI3 state
</span><br><span style="color: hsl(120, 100%, 40%);">+ The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Heci3Enabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014E
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace4;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014F - PCHHOT# pin
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHotEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0150 - SATA LED
</span><br><span style="color: hsl(120, 100%, 40%);">+ SATA LED indicating SATA controller activity. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataLedEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0151 - VRAlert# Pin
</span><br><span style="color: hsl(120, 100%, 40%);">+ When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
</span><br><span style="color: hsl(120, 100%, 40%);">+ to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmVrAlert;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0152 - SLP_S0 VM Dynamic Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS0VmRuntimeControl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0153 - SLP_S0 VM 0.70V Support
</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS0Vm070VSupport;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0154 - SLP_S0 VM 0.75V Support
</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS0Vm075VSupport;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0155 - AMT Switch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AmtEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0156 - WatchDog Timer Switch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WatchDog;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0157 - ASF Switch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AsfEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0158 - Manageability Mode set by Mebx
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ManageabilityMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0159 - PET Progress
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
</span><br><span style="color: hsl(120, 100%, 40%);">+ PET Events.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FwProgress;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x015A - SOL Switch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AmtSolEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x015B - OS Timer
</span><br><span style="color: hsl(120, 100%, 40%);">+ 16 bits Value, Set OS watchdog timer.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 WatchDogTimerOs;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x015D - BIOS Timer
</span><br><span style="color: hsl(120, 100%, 40%);">+ 16 bits Value, Set BIOS watchdog timer.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 WatchDogTimerBios;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x015F - Remote Assistance Trigger Availablilty
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RemoteAssistance;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0160 - KVM Switch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AmtKvmEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0161 - MEBX execution
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Force MEBX execution
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ForcMebxSyncUp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0162
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace5[1];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0163 - PCH PCIe root port connection type
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: built-in device, 1:slot
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSlotImplemented[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x017B - Usage type for ClkSrc
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
</span><br><span style="color: hsl(120, 100%, 40%);">+ (free running), 0xFF: not used
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieClkSrcUsage[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x018B - ClkReq-to-ClkSrc mapping
</span><br><span style="color: hsl(120, 100%, 40%);">+ Number of ClkReq signal assigned to ClkSrc
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieClkSrcClkReq[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x019B - PCIE RP Access Control Services Extended Capability
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable PCIE RP Access Control Services Extended Capability
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpAcsEnabled[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01B3 - PCIE RP Clock Power Management
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
</span><br><span style="color: hsl(120, 100%, 40%);">+ can still be controlled by L1 PM substates mechanism
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpEnableCpm[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01CB - PCIE RP Detect Timeout Ms
</span><br><span style="color: hsl(120, 100%, 40%);">+ The number of milliseconds within 0~65535 in reference code will wait for link to
</span><br><span style="color: hsl(120, 100%, 40%);">+ exit Detect state for enabled ports before assuming there is no device and potentially
</span><br><span style="color: hsl(120, 100%, 40%);">+ disabling the port.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpDetectTimeoutMs[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH-H. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmcModPhySusPgEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01FC - SlpS0WithGbeSupport
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlpS0WithGbeSupport;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01FD
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace6[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0200 - Enable/Disable SA CRID
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: SA CRID, Disable (Default): SA CRID
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CridEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0201 - DMI ASPM
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:L0s, 2:L1, 3:L0sL1
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiAspm;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0202 - PCIe DeEmphasis control per root port
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: -6dB, 1(Default): -3.5dB
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:-6dB, 1:-3.5dB
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegDeEmphasis[4];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0206 - PCIe Slot Power Limit value per root port
</span><br><span style="color: hsl(120, 100%, 40%);">+ Slot power limit value per root port
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegSlotPowerLimitValue[4];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020A - PCIe Slot Power Limit scale per root port
</span><br><span style="color: hsl(120, 100%, 40%);">+ Slot power limit scale per root port
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegSlotPowerLimitScale[4];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020E - PCIe Physical Slot Number per root port
</span><br><span style="color: hsl(120, 100%, 40%);">+ Physical Slot Number per root port
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PegPhysicalSlotNumber[4];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0216 - Enable/Disable PavpEnable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PavpEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0217 - CdClock Frequency selection
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CdClock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PeiGraphicsPeimInit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0219
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace7;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021A - Enable or disable GNA device
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GnaEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable/Clear, 1=Enable/Set
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 X2ApicOptOut;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021C - Base addresses for VT-d function MMIO access
</span><br><span style="color: hsl(120, 100%, 40%);">+ Base addresses for VT-d MMIO access per VT-d engine
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VtdBaseAddress[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0228 - Enable or disable eDP device
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortEdp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0229 - Enable or disable HPD of DDI port B
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortBHpd;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022A - Enable or disable HPD of DDI port C
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortCHpd;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022B - Enable or disable HPD of DDI port D
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortDHpd;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022C - Enable or disable HPD of DDI port F
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortFHpd;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022D - Enable or disable DDC of DDI port B
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortBDdc;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022E - Enable or disable DDC of DDI port C
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortCDdc;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022F - Enable or disable DDC of DDI port D
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortDDdc;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0230 - Enable or disable DDC of DDI port F
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Disable, 1=Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortFDdc;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0231 - Enable/Disable SkipS3CdClockInit
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
</span><br><span style="color: hsl(120, 100%, 40%);">+ CD clock in S3 resume due to GOP absent
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipS3CdClockInit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms
</span><br><span style="color: hsl(120, 100%, 40%);">+ Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
</span><br><span style="color: hsl(120, 100%, 40%);">+ T12 Delay to max 500ms
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DeltaT12PowerCycleDelay;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0234 - Blt Buffer Address
</span><br><span style="color: hsl(120, 100%, 40%);">+ Address of Blt buffer
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BltBufferAddress;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0238 - Blt Buffer Size
</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BltBufferSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x023C - SaPostMemProductionRsvd
</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for SA Post-Mem Production
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaPostMemProductionRsvd[35];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
</span><br><span style="color: hsl(120, 100%, 40%);">+ Alpine ridge
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRootPortGen2PllL1CgDisable[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0277 - Advanced Encryption Standard (AES) feature
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AesEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0278 - Power State 3 enable/disable
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ For all VR Indexes
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Psi3Enable[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x027D - Power State 4 enable/disable
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
</span><br><span style="color: hsl(120, 100%, 40%);">+ all VR Indexes
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Psi4Enable[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0282 - Imon slope correction
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ImonSlope[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0287 - Imon offset correction
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ImonOffset[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x028C - Enable/Disable BIOS configuration of VR
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VrConfigEnable[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0291 - Thermal Design Current enable/disable
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable.For all VR Indexes
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TdcEnable[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0296 - HECI3 state
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
</span><br><span style="color: hsl(120, 100%, 40%);">+ , 8 - 8ms , 10 - 10ms.For all VR Indexe
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TdcTimeWindow[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x029B - Thermal Design Current Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
</span><br><span style="color: hsl(120, 100%, 40%);">+ all VR Indexes
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TdcLock[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A0 - Platform Psys slope correction
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1/100 increment values. Range is 0-200. 125 = 1.25
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysSlope;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A1 - Platform Psys offset correction
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0-255. Value of 100 = 100/4 = 25 offset
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysOffset;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A2 - Acoustic Noise Mitigation feature
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program
</span><br><span style="color: hsl(120, 100%, 40%);">+ slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:
</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled</b>; 1: Enabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AcousticNoiseMitigation;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain
</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
</span><br><span style="color: hsl(120, 100%, 40%);">+ feature enabled. <b>0: False</b>; 1: True
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FastPkgCRampDisableIa;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain
</span><br><span style="color: hsl(120, 100%, 40%);">+ Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
</span><br><span style="color: hsl(120, 100%, 40%);">+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlowSlewRateForIa;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain
</span><br><span style="color: hsl(120, 100%, 40%);">+ Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
</span><br><span style="color: hsl(120, 100%, 40%);">+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlowSlewRateForGt;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain
</span><br><span style="color: hsl(120, 100%, 40%);">+ Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
</span><br><span style="color: hsl(120, 100%, 40%);">+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlowSlewRateForSa;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A7 - Thermal Design Current current limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 TdcPowerLimit[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02B1 - AcLoadline
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 AcLoadline[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02BB
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace8[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02C5 - DcLoadline
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DcLoadline[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02CF - Power State 1 Threshold current
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Psi1Threshold[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02D9 - Power State 2 Threshold current
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Psi2Threshold[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02E3 - Power State 3 Threshold current
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Psi3Threshold[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02ED - Icc Max limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 IccMax[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02F7 - VR Voltage Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 VrVoltageLimit[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain
</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
</span><br><span style="color: hsl(120, 100%, 40%);">+ feature enabled. <b>0: False</b>; 1: True
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FastPkgCRampDisableGt;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
</span><br><span style="color: hsl(120, 100%, 40%);">+ feature enabled. <b>0: False</b>; 1: True
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FastPkgCRampDisableSa;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0303 - Enable VR specific mailbox command
</span><br><span style="color: hsl(120, 100%, 40%);">+ VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
</span><br><span style="color: hsl(120, 100%, 40%);">+ VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
</span><br><span style="color: hsl(120, 100%, 40%);">+ command sent for PS4 exit issue. 11b - Reserved.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SendVrMbxCmd;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0304 - Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved2;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0305 - Enable or Disable TXT
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TxtEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0306
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace9[6];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization
</span><br><span style="color: hsl(120, 100%, 40%);">+ @deprecated SkipMpInit has been moved to FspmUpd
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipMpInit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x030D - McIVR RFI Frequency Prefix
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:
</span><br><span style="color: hsl(120, 100%, 40%);">+ Minus (-).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 McivrRfiFrequencyPrefix;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x030E - McIVR RFI Frequency Adjustment
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in
</span><br><span style="color: hsl(120, 100%, 40%);">+ increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 McivrRfiFrequencyAdjust;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x030F - FIVR RFI Frequency
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-1535 (Up to 153.5MHz) for 19MHz clock.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 FivrRfiFrequency;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0311 - McIVR RFI Spread Spectrum
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 McivrSpreadSpectrum;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0312 - FIVR RFI Spread Spectrum
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range: 0.0% to 10.0% (0-100).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FivrSpreadSpectrum;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain
</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
</span><br><span style="color: hsl(120, 100%, 40%);">+ feature enabled. <b>0: False</b>; 1: True
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FastPkgCRampDisableFivr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain
</span><br><span style="color: hsl(120, 100%, 40%);">+ Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic
</span><br><span style="color: hsl(120, 100%, 40%);">+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlowSlewRateForFivr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0315 - CpuBistData
</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer CPU BIST Data
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CpuBistData;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
</span><br><span style="color: hsl(120, 100%, 40%);">+ command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IslVrCmd;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x031A - Imon slope1 correction
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 ImonSlope1[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0324 - CPU VR Power Delivery Design
</span><br><span style="color: hsl(120, 100%, 40%);">+ Used to communicate the power delivery design capability of the board. This value
</span><br><span style="color: hsl(120, 100%, 40%);">+ is an enum of the available power delivery segments that are defined in the Platform
</span><br><span style="color: hsl(120, 100%, 40%);">+ Design Guide.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VrPowerDeliveryDesign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0328 - Pre Wake Randomization time
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization
</span><br><span style="color: hsl(120, 100%, 40%);">+ time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0-255 <b>0</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PreWake;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0329 - Ramp Up Randomization time
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization
</span><br><span style="color: hsl(120, 100%, 40%);">+ time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-255 <b>0</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RampUp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x032A - Ramp Down Randomization time
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization
</span><br><span style="color: hsl(120, 100%, 40%);">+ time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-255 <b>0</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RampDown;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x032B - CpuMpPpi
</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer for CpuMpPpi
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CpuMpPpi;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x032F - CpuMpHob
</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CpuMpHob;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0333 - Enable or Disable processor debug features
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DebugInterfaceEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0334 - ReservedCpuPostMemProduction
</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for CPU Post-Mem Production
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedCpuPostMemProduction[18];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0346 - Enable DMI ASPM
</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchDmiAspm;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0347 - Enable Power Optimizer
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable DMI Power Optimizer on PCH side.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPwrOptEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0348 - PCH Flash Protection Ranges Write Enble
</span><br><span style="color: hsl(120, 100%, 40%);">+ Write or erase is blocked by hardware.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchWriteProtectionEnable[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x034D - PCH Flash Protection Ranges Read Enble
</span><br><span style="color: hsl(120, 100%, 40%);">+ Read is blocked by hardware.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchReadProtectionEnable[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0352 - PCH Protect Range Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
</span><br><span style="color: hsl(120, 100%, 40%);">+ limit comparison.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchProtectedRangeLimit[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x035C - PCH Protect Range Base
</span><br><span style="color: hsl(120, 100%, 40%);">+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchProtectedRangeBase[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0366 - Enable Pme
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Azalia wake-on-ring.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaPme;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0367
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace10;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0368 - VC Type
</span><br><span style="color: hsl(120, 100%, 40%);">+ Virtual Channel Type Select: 0: VC0, 1: VC1.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: VC0, 1: VC1
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaVcType;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0369 - HD Audio Link Frequency
</span><br><span style="color: hsl(120, 100%, 40%);">+ HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 6MHz, 1: 12MHz, 2: 24MHz
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaLinkFrequency;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036A - iDisp-Link Frequency
</span><br><span style="color: hsl(120, 100%, 40%);">+ iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 4: 96MHz, 3: 48MHz
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaIDispLinkFrequency;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036B - iDisp-Link T-mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 2T, 1: 1T
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaIDispLinkTmode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
</span><br><span style="color: hsl(120, 100%, 40%);">+ driver or SST driver supported).
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaDspUaaCompliance;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036D - iDisplay Audio Codec disconnection
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaIDispCodecDisconnect;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036E - USB LFPS Filter selection
</span><br><span style="color: hsl(120, 100%, 40%);">+ For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUsbHsioFilterSel[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0378
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace11[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x037D - Enable PCH Io Apic Entry 24-119
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIoApicEntry24_119;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x037E - PCH Io Apic ID
</span><br><span style="color: hsl(120, 100%, 40%);">+ This member determines IOAPIC ID. Default is 0x02.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIoApicId;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x037F
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace12;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshSpiGpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshUart0GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshUart1GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshI2c0GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshI2c1GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshI2c2GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp0GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp1GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp2GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp3GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp4GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp5GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp6GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp7GpioAssign;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038E - PCH ISH PDT Unlock Msg
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: False; 1: True.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshPdtUnlock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLanLtrEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0390
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace13[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
</span><br><span style="color: hsl(120, 100%, 40%);">+ protection.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLockDownBiosLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0394 - PCH Compatibility Revision ID
</span><br><span style="color: hsl(120, 100%, 40%);">+ This member describes whether or not the CRID feature of PCH should be enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchCrid;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0395 - RTC CMOS MEMORY LOCK
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
</span><br><span style="color: hsl(120, 100%, 40%);">+ and and lower 128-byte bank of RTC RAM.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLockDownRtcMemoryLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0396 - Enable PCIE RP HotPlug
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the root port is hot plug available.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpHotPlug[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AE - Enable PCIE RP Pm Sci
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the root port power manager SCI is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpPmSci[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C6 - Enable PCIE RP Ext Sync
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the extended synch is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpExtSync[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Transmitter Half Swing is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpTransmitterHalfSwing[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03F6 - Enable PCIE RP Clk Req Detect
</span><br><span style="color: hsl(120, 100%, 40%);">+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpClkReqDetect[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x040E - PCIE RP Advanced Error Report
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Advanced Error Reporting is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpAdvancedErrorReporting[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0426 - PCIE RP Unsupported Request Report
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Unsupported Request Report is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpUnsupportedRequestReport[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x043E - PCIE RP Fatal Error Report
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Fatal Error Report is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpFatalErrorReport[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0456 - PCIE RP No Fatal Error Report
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the No Fatal Error Report is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpNoFatalErrorReport[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x046E - PCIE RP Correctable Error Report
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Correctable Error Report is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpCorrectableErrorReport[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0486 - PCIE RP System Error On Fatal Error
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the System Error on Fatal Error is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSystemErrorOnFatalError[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x049E - PCIE RP System Error On Non Fatal Error
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the System Error on Non Fatal Error is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSystemErrorOnNonFatalError[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04B6 - PCIE RP System Error On Correctable Error
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the System Error on Correctable Error is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSystemErrorOnCorrectableError[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04CE - PCIE RP Max Payload
</span><br><span style="color: hsl(120, 100%, 40%);">+ Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpMaxPayload[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters
</span><br><span style="color: hsl(120, 100%, 40%);">+ Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for
</span><br><span style="color: hsl(120, 100%, 40%);">+ controlling the input offset
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUsbHsioRxTuningParameters[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUsbHsioRxTuningEnable[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FA
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace14[4];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FE - PCIE RP Pcie Speed
</span><br><span style="color: hsl(120, 100%, 40%);">+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_SPEED).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpPcieSpeed[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: hardware equalization; 4: Fixed Coeficients.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpGen3EqPh3Method[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x052E - PCIE RP Physical Slot Number
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates the slot number for the root port. Default is the value as root port index.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpPhysicalSlotNumber[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0546 - PCIE RP Completion Timeout
</span><br><span style="color: hsl(120, 100%, 40%);">+ The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpCompletionTimeout[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x055E
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace15[106];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05C8 - PCIE RP Aspm
</span><br><span style="color: hsl(120, 100%, 40%);">+ The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
</span><br><span style="color: hsl(120, 100%, 40%);">+ PchPcieAspmAutoConfig.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpAspm[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05E0 - PCIE RP L1 Substates
</span><br><span style="color: hsl(120, 100%, 40%);">+ The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
</span><br><span style="color: hsl(120, 100%, 40%);">+ Default is PchPcieL1SubstatesL1_1_2.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpL1Substates[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05F8 - PCIE RP Ltr Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting Mechanism.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpLtrEnable[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0610 - PCIE RP Ltr Config Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpLtrConfigLock[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieEqPh3LaneParamCm[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieEqPh3LaneParamCp[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0658 - PCIE Sw Eq CoeffList Cm
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_EQ_PARAM. Coefficient C-1.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieSwEqCoeffListCm[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x065D - PCIE Sw Eq CoeffList Cp
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_EQ_PARAM. Coefficient C+1.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieSwEqCoeffListCp[5];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0662 - PCIE Disable RootPort Clock Gating
</span><br><span style="color: hsl(120, 100%, 40%);">+ Describes whether the PCI Express Clock Gating for each root port is enabled by
</span><br><span style="color: hsl(120, 100%, 40%);">+ platform modules. 0: Disable; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieDisableRootPortClockGating;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0663 - PCIE Enable Peer Memory Write
</span><br><span style="color: hsl(120, 100%, 40%);">+ This member describes whether Peer Memory Writes are enabled on the platform.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieEnablePeerMemoryWrite;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0664
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace16;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0665 - PCIE Compliance Test Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Compliance Test Mode shall be enabled when using Compliance Load Board.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieComplianceTestMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0666 - PCIE Rp Function Swap
</span><br><span style="color: hsl(120, 100%, 40%);">+ Allows BIOS to use root port function number swapping when root port of function
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 is disabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpFunctionSwap;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0667 - Teton Glacier Support
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables support for the Teton Glacier card.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TetonGlacierSupport;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0668 - Teton Glacier Cycle Router
</span><br><span style="color: hsl(120, 100%, 40%);">+ Specify to which cycle router Teton Glacier is connected, it is valid only when
</span><br><span style="color: hsl(120, 100%, 40%);">+ Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TetonGlacierCR;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+ When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPmeB0S5Dis;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x066A - SPI ChipSelect signal polarity
</span><br><span style="color: hsl(120, 100%, 40%);">+ Selects SPI ChipSelect signal polarity.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoSpiCsPolarity[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x066D - PCIE IMR
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables Isolated Memory Region for PCIe.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpImrEnabled;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x066E - PCIE IMR port number
</span><br><span style="color: hsl(120, 100%, 40%);">+ Selects PCIE root port number for IMR feature.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpImrSelection;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x066F
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace17;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0670 - PCH Pm Wol Enable Override
</span><br><span style="color: hsl(120, 100%, 40%);">+ Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmWolEnableOverride;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx
</span><br><span style="color: hsl(120, 100%, 40%);">+ Determine if enable PCIe to wake from deep Sx.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPcieWakeFromDeepSx;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0672 - PCH Pm WoW lan Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmWoWlanEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
</span><br><span style="color: hsl(120, 100%, 40%);">+ PWRM_CFG3 register.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmWoWlanDeepSxEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0674 - PCH Pm Lan Wake From DeepSx
</span><br><span style="color: hsl(120, 100%, 40%);">+ Determine if enable LAN to wake from deep Sx.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmLanWakeFromDeepSx;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0675 - PCH Pm Deep Sx Pol
</span><br><span style="color: hsl(120, 100%, 40%);">+ Deep Sx Policy.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmDeepSxPol;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0676 - PCH Pm Slp S3 Min Assert
</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS3MinAssert;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0677 - PCH Pm Slp S4 Min Assert
</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS4MinAssert;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0678 - PCH Pm Slp Sus Min Assert
</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpSusMinAssert;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0679 - PCH Pm Slp A Min Assert
</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpAMinAssert;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x067A - SLP_S0# Override
</span><br><span style="color: hsl(120, 100%, 40%);">+ Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'
</span><br><span style="color: hsl(120, 100%, 40%);">+ will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion
</span><br><span style="color: hsl(120, 100%, 40%);">+ when debug is enabled. \n
</span><br><span style="color: hsl(120, 100%, 40%);">+ Note: This BIOS option should keep 'Auto', other options are intended for advanced
</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration only.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:Enabled, 2:Auto
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlpS0Override;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x067B - S0ix Override Settings
</span><br><span style="color: hsl(120, 100%, 40%);">+ Select 'Auto', it will be auto-configured according to probe type. 'No Change' will
</span><br><span style="color: hsl(120, 100%, 40%);">+ keep PMC default settings. Or select the desired debug probe type for S0ix Override
</span><br><span style="color: hsl(120, 100%, 40%);">+ settings.\n
</span><br><span style="color: hsl(120, 100%, 40%);">+ Reminder: DCI OOB (aka BSSB) uses CCA probe.\n
</span><br><span style="color: hsl(120, 100%, 40%);">+ Note: This BIOS option should keep 'Auto', other options are intended for advanced
</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration only.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlpS0DisQForDebug;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x067C - USB Overcurrent Override for DbC
</span><br><span style="color: hsl(120, 100%, 40%);">+ This option overrides USB Over Current enablement state that USB OC will be disabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ after enabling this option. Enable when DbC is used to avoid signaling conflicts.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchEnableDbcObs;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x067D
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace18[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0680 - PCH Pm Lpc Clock Run
</span><br><span style="color: hsl(120, 100%, 40%);">+ This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Default value is Disabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmLpcClockRun;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0681 - PCH Pm Slp Strch Sus Up
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SLP_X Stretching After SUS Well Power Up.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpStrchSusUp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0682 - PCH Pm Slp Lan Low Dc
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable SLP_LAN# Low on DC Power.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpLanLowDc;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0683 - PCH Pm Pwr Btn Override Period
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPwrBtnOverridePeriod;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown
</span><br><span style="color: hsl(120, 100%, 40%);">+ When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmDisableDsxAcPresentPulldown;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0685
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace19;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0686 - PCH Pm Disable Native Power Button
</span><br><span style="color: hsl(120, 100%, 40%);">+ Power button native mode disable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmDisableNativePowerButton;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0687 - PCH Pm Slp S0 Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS0Enable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0688 - PCH Pm ME_WAKE_STS
</span><br><span style="color: hsl(120, 100%, 40%);">+ Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmMeWakeSts;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS
</span><br><span style="color: hsl(120, 100%, 40%);">+ Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmWolOvrWkSts;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068A - PCH Pm Reset Power Cycle Duration
</span><br><span style="color: hsl(120, 100%, 40%);">+ Could be customized in the unit of second. Please refer to EDS for all support settings.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 is default, 1 is 1 second, 2 is 2 seconds, ...
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPwrCycDur;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068B - PCH Pm Pcie Pll Ssc
</span><br><span style="color: hsl(120, 100%, 40%);">+ Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
</span><br><span style="color: hsl(120, 100%, 40%);">+ BIOS override.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPciePllSsc;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068C
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace20;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068D - PCH Sata Pwr Opt Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ SATA Power Optimizer on PCH side.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPwrOptEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068E - PCH Sata eSATA Speed Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EsataSpeedLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068F - PCH Sata Speed Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataSpeedLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0690 - Enable SATA Port HotPlug
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SATA Port HotPlug.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsHotPlug[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0698 - Enable SATA Port Interlock Sw
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SATA Port Interlock Sw.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsInterlockSw[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06A0 - Enable SATA Port External
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SATA Port External.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsExternal[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06A8 - Enable SATA Port SpinUp
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the COMRESET initialization Sequence to the device.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsSpinUp[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06B0 - Enable SATA Port Solid State Drive
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: HDD; 1: SSD.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsSolidStateDrive[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06B8 - Enable SATA Port Enable Dito Config
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsEnableDitoConfig[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06C0 - Enable SATA Port DmVal
</span><br><span style="color: hsl(120, 100%, 40%);">+ DITO multiplier. Default is 15.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsDmVal[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06C8 - Enable SATA Port DmVal
</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVSLP Idle Timeout (DITO), Default is 625.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 SataPortsDitoVal[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06D8 - Enable SATA Port ZpOdd
</span><br><span style="color: hsl(120, 100%, 40%);">+ Support zero power ODD.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsZpOdd[8];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E0 - PCH Sata Rst Raid Device Id
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable RAID Alternate ID.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Client, 1:Alternate, 2:Server
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaidDeviceId;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E1 - PCH Sata Rst Raid0
</span><br><span style="color: hsl(120, 100%, 40%);">+ RAID0.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaid0;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E2 - PCH Sata Rst Raid1
</span><br><span style="color: hsl(120, 100%, 40%);">+ RAID1.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaid1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E3 - PCH Sata Rst Raid10
</span><br><span style="color: hsl(120, 100%, 40%);">+ RAID10.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaid10;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E4 - PCH Sata Rst Raid5
</span><br><span style="color: hsl(120, 100%, 40%);">+ RAID5.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaid5;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E5 - PCH Sata Rst Irrt
</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Rapid Recovery Technology.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstIrrt;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner
</span><br><span style="color: hsl(120, 100%, 40%);">+ OROM UI and BANNER.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstOromUiBanner;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay
</span><br><span style="color: hsl(120, 100%, 40%);">+ 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstOromUiDelay;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E8 - PCH Sata Rst Hdd Unlock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates that the HDD password unlock in the OS is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstHddUnlock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E9 - PCH Sata Rst Led Locate
</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
</span><br><span style="color: hsl(120, 100%, 40%);">+ enabled on the OS.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstLedLocate;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06EA - PCH Sata Rst Irrt Only
</span><br><span style="color: hsl(120, 100%, 40%);">+ Allow only IRRT drives to span internal and external ports.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstIrrtOnly;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06EB - PCH Sata Rst Smart Storage
</span><br><span style="color: hsl(120, 100%, 40%);">+ RST Smart Storage caching Bit.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstSmartStorage;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Intel RST for PCIe Storage remapping.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstPcieEnable[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06EF - PCH Sata Rst Pcie Storage Port
</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstPcieStoragePort[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstPcieDeviceResetDelay[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F5 - Enable eMMC HS400 Training
</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400TuningRequired;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F6 - Set HS400 Tuning Data Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Set if HS400 Tuning Data Valid.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400DllDataValid;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F7 - Rx Strobe Delay Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400RxStrobeDll1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F8 - Tx Data Delay Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400TxDataDll;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F9 - I/O Driver Strength
</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:33 Ohm, 1:40 Ohm, 2:50 Ohm
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400DriverStrength;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06FA - PCH SerialIo I2C Pads Termination
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
</span><br><span style="color: hsl(120, 100%, 40%);">+ pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
</span><br><span style="color: hsl(120, 100%, 40%);">+ for I2C1, and so on.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSerialIoI2cPadsTermination[6];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0700
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace21;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0701 - PcdSerialIoUart0PinMuxing
</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:default pins, 1:pins muxed with CNV_BRI/RGI
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoUart0PinMuxing;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0702
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace22[1];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables UART hardware flow control, CTS and RTS linesh.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoUartHwFlowCtrl[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0706 - UART Number For Debug Purpose
</span><br><span style="color: hsl(120, 100%, 40%);">+ UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected
</span><br><span style="color: hsl(120, 100%, 40%);">+ as CNVi BT Core interface, it cannot be used for debug purpose.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:UART0, 1:UART1, 2:UART2
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoDebugUartNumber;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0707 - Enable Debug UART Controller
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable debug UART controller after post.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoEnableDebugUartAfterPost;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0708 - Enable Serial IRQ
</span><br><span style="color: hsl(120, 100%, 40%);">+ Determines if enable Serial IRQ.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSirqEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0709 - Serial IRQ Mode Select
</span><br><span style="color: hsl(120, 100%, 40%);">+ Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSirqMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070A - Start Frame Pulse Width
</span><br><span style="color: hsl(120, 100%, 40%);">+ Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchStartFramePulse;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070B - Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedForFuture1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070C - Thermal Device SMI Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ This locks down SMI Enable on Alert Thermal Sensor Trip.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTsmicLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070D - Thermal Throttling Custimized T0Level Value
</span><br><span style="color: hsl(120, 100%, 40%);">+ Custimized T0Level value.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchT0Level;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070F - Thermal Throttling Custimized T1Level Value
</span><br><span style="color: hsl(120, 100%, 40%);">+ Custimized T1Level value.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchT1Level;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0711 - Thermal Throttling Custimized T2Level Value
</span><br><span style="color: hsl(120, 100%, 40%);">+ Custimized T2Level value.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchT2Level;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0713 - Enable The Thermal Throttle
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the thermal throttle function.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTTEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0714 - PMSync State 13
</span><br><span style="color: hsl(120, 100%, 40%);">+ When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
</span><br><span style="color: hsl(120, 100%, 40%);">+ at least T2 state.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTTState13Enable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0715 - Thermal Throttle Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Throttle Lock.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTTLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0716 - Thermal Throttling Suggested Setting
</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Throttling Suggested Setting.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TTSuggestedSetting;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0717 - Enable PCH Cross Throttling
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable PCH Cross Throttling
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TTCrossThrottling;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ DMI Thermal Sensor Autonomous Width Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchDmiTsawEn;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0719 - DMI Thermal Sensor Suggested Setting
</span><br><span style="color: hsl(120, 100%, 40%);">+ DMT thermal sensor suggested representative values.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiSuggestedSetting;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071A - Thermal Sensor 0 Target Width
</span><br><span style="color: hsl(120, 100%, 40%);">+ DMT thermal sensor suggested representative values.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiTS0TW;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071B - Thermal Sensor 1 Target Width
</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Sensor 1 Target Width.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiTS1TW;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071C - Thermal Sensor 2 Target Width
</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Sensor 2 Target Width.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiTS2TW;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071D - Thermal Sensor 3 Target Width
</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Sensor 3 Target Width.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiTS3TW;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071E - Port 0 T1 Multipler
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 T1 Multipler.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0T1M;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071F - Port 0 T2 Multipler
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 T2 Multipler.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0T2M;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0720 - Port 0 T3 Multipler
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 T3 Multipler.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0T3M;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0721 - Port 0 Tdispatch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 Tdispatch.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0TDisp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0722 - Port 1 T1 Multipler
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 T1 Multipler.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1T1M;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0723 - Port 1 T2 Multipler
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 T2 Multipler.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1T2M;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0724 - Port 1 T3 Multipler
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 T3 Multipler.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1T3M;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0725 - Port 1 Tdispatch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 Tdispatch.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1TDisp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0726 - Port 0 Tinactive
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 Tinactive.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0Tinact;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 Alternate Fast Init Tdispatch.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0TDispFinit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0728 - Port 1 Tinactive
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 Tinactive.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1Tinact;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch
</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 Alternate Fast Init Tdispatch.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1TDispFinit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x072A - Sata Thermal Throttling Suggested Setting
</span><br><span style="color: hsl(120, 100%, 40%);">+ Sata Thermal Throttling Suggested Setting.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataThermalSuggestedSetting;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x072B - Enable Memory Thermal Throttling
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Thermal Throttling.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchMemoryThrottlingEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x072C - Memory Thermal Throttling
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Thermal Throttling.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchMemoryPmsyncEnable[2];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x072E - Enable Memory Thermal Throttling
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Thermal Throttling.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchMemoryC0TransmitEnable[2];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0730 - Enable Memory Thermal Throttling
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Thermal Throttling.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchMemoryPinSelection[2];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0732 - Thermal Device Temperature
</span><br><span style="color: hsl(120, 100%, 40%);">+ Decides the temperature.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchTemperatureHotLevel;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0734 - Enable xHCI Compliance Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Compliance Mode can be enabled for testing through this option but this is disabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ by default.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchEnableComplianceMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0735 - USB2 Port Over Current Pin
</span><br><span style="color: hsl(120, 100%, 40%);">+ Describe the specific over current pin number of USB 2.0 Port N.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2OverCurrentPin[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0745 - USB3 Port Over Current Pin
</span><br><span style="color: hsl(120, 100%, 40%);">+ Describe the specific over current pin number of USB 3.0 Port N.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3OverCurrentPin[10];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x074F - Enable 8254 Static Clock Gating
</span><br><span style="color: hsl(120, 100%, 40%);">+ Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
</span><br><span style="color: hsl(120, 100%, 40%);">+ might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
</span><br><span style="color: hsl(120, 100%, 40%);">+ boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Enable8254ClockGating;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0750 - PCH Sata Rst Optane Memory
</span><br><span style="color: hsl(120, 100%, 40%);">+ Optane Memory
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstOptaneMemory;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0751 - PCH Sata Rst CPU Attached Storage
</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU Attached Storage
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstCpuAttachedStorage;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3
</span><br><span style="color: hsl(120, 100%, 40%);">+ This is only applicable when Enable8254ClockGating is disabled. FSP will do the
</span><br><span style="color: hsl(120, 100%, 40%);">+ 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
</span><br><span style="color: hsl(120, 100%, 40%);">+ avoids the SMI requirement for the programming.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Enable8254ClockGatingOnS3;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0753
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace23;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0754 - Pch PCIE device override table pointer
</span><br><span style="color: hsl(120, 100%, 40%);">+ The PCIe device table is being used to override PCIe device ASPM settings. This
</span><br><span style="color: hsl(120, 100%, 40%);">+ is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
</span><br><span style="color: hsl(120, 100%, 40%);">+ refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
</span><br><span style="color: hsl(120, 100%, 40%);">+ must be 0.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PchPcieDeviceOverrideTablePtr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0758 - Enable TCO timer.
</span><br><span style="color: hsl(120, 100%, 40%);">+ When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
</span><br><span style="color: hsl(120, 100%, 40%);">+ huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
</span><br><span style="color: hsl(120, 100%, 40%);">+ emulation must be enabled, and WDAT table must not be exposed to the OS.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableTcoTimer;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0759 - BgpdtHash[4]
</span><br><span style="color: hsl(120, 100%, 40%);">+ BgpdtHash values
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 BgpdtHash[4];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0779 - BiosGuardAttr
</span><br><span style="color: hsl(120, 100%, 40%);">+ BiosGuardAttr default values
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BiosGuardAttr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x077D - BiosGuardModulePtr
</span><br><span style="color: hsl(120, 100%, 40%);">+ BiosGuardModulePtr default values
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 BiosGuardModulePtr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0785 - SendEcCmd
</span><br><span style="color: hsl(120, 100%, 40%);">+ SendEcCmd function pointer. \n
</span><br><span style="color: hsl(120, 100%, 40%);">+ @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
</span><br><span style="color: hsl(120, 100%, 40%);">+ EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SendEcCmd;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x078D - EcCmdProvisionEav
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EcCmdProvisionEav;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x078E - EcCmdLock
</span><br><span style="color: hsl(120, 100%, 40%);">+ EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EcCmdLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x078F - SgxEpoch0
</span><br><span style="color: hsl(120, 100%, 40%);">+ SgxEpoch0 default values
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SgxEpoch0;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0797 - SgxEpoch1
</span><br><span style="color: hsl(120, 100%, 40%);">+ SgxEpoch1 default values
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SgxEpoch1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x079F - SgxSinitNvsData
</span><br><span style="color: hsl(120, 100%, 40%);">+ SgxSinitNvsData default values
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SgxSinitNvsData;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A0 - Si Config CSM Flag.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Platform specific common policies that used by several silicon components. CSM status flag.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SiCsmFlag;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A1
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 SiSsidTablePtr;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A5
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 SiNumberOfSsidTableEntry;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A7 - SATA RST Interrupt Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Msix, 1:Msi, 2:Legacy
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstInterrupt;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A8 - ME Unconfig on RTC clear
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 2: Cmos is clear, status unkonwn. 3: Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
</span><br><span style="color: hsl(120, 100%, 40%);">+ is clear, 3: Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MeUnconfigOnRtcClear;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A9 - Enable PS_ON.
</span><br><span style="color: hsl(120, 100%, 40%);">+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
</span><br><span style="color: hsl(120, 100%, 40%);">+ target that will be required by the California Energy Commission (CEC). When FALSE,
</span><br><span style="color: hsl(120, 100%, 40%);">+ PS_ON is to be disabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsOnEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
</span><br><span style="color: hsl(120, 100%, 40%);">+ and VccSTG rails instead of SLP_S0# pin.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmcCpuC10GatePinEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AB - Pch Dmi Aspm Ctrl
</span><br><span style="color: hsl(120, 100%, 40%);">+ ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchDmiAspmCtrl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AC
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsUpd[1];
</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_S_CONFIG;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S Test Configuration
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AD
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Signature;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B1 - Enable/Disable Device 7
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Device 7 enabled, Disable (Default): Device 7 disabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChapDeviceEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B2 - Skip PAM register lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM registers will be locked by RC
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipPamLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B3 - EDRAM Test Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM registers will be locked by RC
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EdramTestMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B4 - DMI Extended Sync Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
</span><br><span style="color: hsl(120, 100%, 40%);">+ Sync Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiExtSync;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B5 - DMI IOT Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiIot;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B6 - PEG Max Payload size per root port
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegMaxPayload[4];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BA - Enable/Disable IGFX RenderStandby
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RenderStandby;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BB - Enable/Disable IGFX PmSupport
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmSupport;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BC - Enable/Disable CdynmaxClamp
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CdynmaxClampEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BD - Disable VT-d
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VtdDisable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BE - GT Frequency Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
</span><br><span style="color: hsl(120, 100%, 40%);">+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x18: 1200 Mhz
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
</span><br><span style="color: hsl(120, 100%, 40%);">+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x18: 1200 Mhz
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GtFreqMax;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BF - Disable Turbo GT
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableTurboGt;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07C0 - SaPostMemTestRsvd
</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for SA Post-Mem Test
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaPostMemTestRsvd[11];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CB - 1-Core Ratio Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 8-Core Ratio Limit. Range is 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 OneCoreRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CC - 2-Core Ratio Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TwoCoreRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CD - 3-Core Ratio Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThreeCoreRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CE - 4-Core Ratio Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FourCoreRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CF - Enable or Disable HWP
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ 2-3:Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Hwp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D0 - Hardware Duty Cycle Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HdcControl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D1 - Package Long duration turbo mode time
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40
</span><br><span style="color: hsl(120, 100%, 40%);">+ , 48 , 56 , 64 , 80 , 96 , 112 , 128
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit1Time;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D2 - Short Duration Turbo Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit2;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D3 - Turbo settings Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TurboPowerLimitLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D4 - Package PL3 time window
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL3 time window range for this policy from 0 to 64ms
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit3Time;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D5 - Package PL3 Duty Cycle
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL3 Duty Cycle; Valid Range is 0 to 100
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit3DutyCycle;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D6 - Package PL3 Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit3Lock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D7 - Package PL4 Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit4Lock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D8 - TCC Activation Offset
</span><br><span style="color: hsl(120, 100%, 40%);">+ TCC Activation Offset. Offset from factory set TCC activation temperature at which
</span><br><span style="color: hsl(120, 100%, 40%);">+ the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
</span><br><span style="color: hsl(120, 100%, 40%);">+ Temperature, in volts.For Y SKU, the recommended default for this policy is <b>15</b>,
</span><br><span style="color: hsl(120, 100%, 40%);">+ For all other SKUs the recommended default are <b>0</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TccActivationOffset;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
</span><br><span style="color: hsl(120, 100%, 40%);">+ below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
</span><br><span style="color: hsl(120, 100%, 40%);">+ For all other SKUs the recommended default are <b>0: Disabled</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TccOffsetClamp;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DA - Tcc Offset Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
</span><br><span style="color: hsl(120, 100%, 40%);">+ target; <b>0: Disabled</b>; 1: Enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TccOffsetLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DB - Custom Ratio State Entries
</span><br><span style="color: hsl(120, 100%, 40%);">+ The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
</span><br><span style="color: hsl(120, 100%, 40%);">+ ratio table.Sets the number of custom P-states. At least 2 states must be present
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 NumberOfEntries;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DC - Custom Short term Power Limit time window
</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit time window value for custom CTDP level 1. Valid Range 0
</span><br><span style="color: hsl(120, 100%, 40%);">+ to 128, 0 = AUTO
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom1PowerLimit1Time;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DD - Custom Turbo Activation Ratio
</span><br><span style="color: hsl(120, 100%, 40%);">+ Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom1TurboActivationRatio;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DE - Custom Config Tdp Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom1ConfigTdpControl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DF - Custom Short term Power Limit time window
</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit time window value for custom CTDP level 2. Valid Range 0
</span><br><span style="color: hsl(120, 100%, 40%);">+ to 128, 0 = AUTO
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom2PowerLimit1Time;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E0 - Custom Turbo Activation Ratio
</span><br><span style="color: hsl(120, 100%, 40%);">+ Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom2TurboActivationRatio;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E1 - Custom Config Tdp Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom2ConfigTdpControl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E2 - Custom Short term Power Limit time window
</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit time window value for custom CTDP level 3. Valid Range 0
</span><br><span style="color: hsl(120, 100%, 40%);">+ to 128, 0 = AUTO
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom3PowerLimit1Time;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E3 - Custom Turbo Activation Ratio
</span><br><span style="color: hsl(120, 100%, 40%);">+ Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom3TurboActivationRatio;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E4 - Custom Config Tdp Control
</span><br><span style="color: hsl(120, 100%, 40%);">+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom3ConfigTdpControl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E5 - ConfigTdp mode settings Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ConfigTdpLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E6 - Load Configurable TDP SSDT
</span><br><span style="color: hsl(120, 100%, 40%);">+ Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ConfigTdpBios;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E7 - PL1 Enable value
</span><br><span style="color: hsl(120, 100%, 40%);">+ PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysPowerLimit1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E8 - PL1 timewindow
</span><br><span style="color: hsl(120, 100%, 40%);">+ PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds)
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysPowerLimit1Time;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E9 - PL2 Enable Value
</span><br><span style="color: hsl(120, 100%, 40%);">+ PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysPowerLimit2;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MlcStreamerPrefetcher;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MlcSpatialPrefetcher;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MonitorMwaitEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07ED - Enable or Disable initialization of machine check registers
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MachineCheckEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features
</span><br><span style="color: hsl(120, 100%, 40%);">+ @deprecated Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DebugInterfaceEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EF - Lock or Unlock debug interface features
</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DebugInterfaceLockEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07F0 - AP Idle Manner of waiting for SIPI
</span><br><span style="color: hsl(120, 100%, 40%);">+ AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: HALT loop, 2: MWAIT loop, 3: RUN loop
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ApIdleManner;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07F1 - Control on Processor Trace output scheme
</span><br><span style="color: hsl(120, 100%, 40%);">+ Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Single Range Output, 1: ToPA Output
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcessorTraceOutputScheme;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07F2 - Enable or Disable Processor Trace feature
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcessorTraceEnable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07F3 - Base of memory region allocated for Processor Trace
</span><br><span style="color: hsl(120, 100%, 40%);">+ Base address of memory region allocated for Processor Trace. Processor Trace requires
</span><br><span style="color: hsl(120, 100%, 40%);">+ 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 ProcessorTraceMemBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07FB - Memory region allocation for Processor Trace
</span><br><span style="color: hsl(120, 100%, 40%);">+ Length in bytes of memory region allocated for Processor Trace. Processor Trace
</span><br><span style="color: hsl(120, 100%, 40%);">+ requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 ProcessorTraceMemLength;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07FF - Enable or Disable Voltage Optimization feature
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VoltageOptimization;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Eist;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0801 - Enable or Disable Energy Efficient P-state
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnergyEfficientPState;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0802 - Enable or Disable Energy Efficient Turbo
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnergyEfficientTurbo;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0803 - Enable or Disable T states
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TStates;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT#
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BiProcHot;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableProcHotOut;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0806 - Enable or Disable PROCHOT# Response
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcHotResponse;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0807 - Enable or Disable VR Thermal Alert
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableVrThermalAlert;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0808 - Enable or Disable Thermal Reporting
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AutoThermalReporting;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0809 - Enable or Disable Thermal Monitor
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThermalMonitor;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080A - Enable or Disable CPU power states (C-states)
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Cx;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080B - Configure C-State Configuration Lock
</span><br><span style="color: hsl(120, 100%, 40%);">+ Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmgCstCfgCtrlLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080C - Enable or Disable Enhanced C-states
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C1e;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080D - Enable or Disable Package Cstate Demotion
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PkgCStateDemotion;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080E - Enable or Disable Package Cstate UnDemotion
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PkgCStateUnDemotion;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080F - Enable or Disable CState-Pre wake
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CStatePreWake;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0810 - Enable or Disable TimedMwait Support.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TimedMwait;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0811 - Enable or Disable IO to MWAIT redirection
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstCfgCtrIoMwaitRedirection;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0812 - Set the Max Pkg Cstate
</span><br><span style="color: hsl(120, 100%, 40%);">+ Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
</span><br><span style="color: hsl(120, 100%, 40%);">+ C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
</span><br><span style="color: hsl(120, 100%, 40%);">+ 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PkgCStateLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0813 - TimeUnit for C-State Latency Control0
</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl0TimeUnit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0814 - TimeUnit for C-State Latency Control1
</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl1TimeUnit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0815 - TimeUnit for C-State Latency Control2
</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl2TimeUnit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0816 - TimeUnit for C-State Latency Control3
</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl3TimeUnit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0817 - TimeUnit for C-State Latency Control4
</span><br><span style="color: hsl(120, 100%, 40%);">+ Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl4TimeUnit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0818 - TimeUnit for C-State Latency Control5
</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl5TimeUnit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0819 - Interrupt Redirection Mode Select
</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
</span><br><span style="color: hsl(120, 100%, 40%);">+ PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PpmIrmSetting;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081A - Lock prochot configuration
</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcHotLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081B - Configuration for boot TDP selection
</span><br><span style="color: hsl(120, 100%, 40%);">+ Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
</span><br><span style="color: hsl(120, 100%, 40%);">+ Up;0xFF : Deactivate
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ConfigTdpLevel;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081C - Race To Halt
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
</span><br><span style="color: hsl(120, 100%, 40%);">+ in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
</span><br><span style="color: hsl(120, 100%, 40%);">+ through MSR 1FC bit 20)Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaceToHalt;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081D - Max P-State Ratio
</span><br><span style="color: hsl(120, 100%, 40%);">+ Max P-State Ratio, Valid Range 0 to 0x7F
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MaxRatio;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081E - P-state ratios for custom P-state table
</span><br><span style="color: hsl(120, 100%, 40%);">+ P-state ratios for custom P-state table. NumberOfEntries has valid range between
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
</span><br><span style="color: hsl(120, 100%, 40%);">+ are configurable. Valid Range of each entry is 0 to 0x7F
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 StateRatio[40];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table
</span><br><span style="color: hsl(120, 100%, 40%);">+ P-state ratios for max 16 version of custom P-state table. This table is used for
</span><br><span style="color: hsl(120, 100%, 40%);">+ OS versions limited to a max of 16 P-States. If the first entry of this table is
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, or if Number of Entries is 16 or less, then this table will be ignored, and
</span><br><span style="color: hsl(120, 100%, 40%);">+ up to the top 16 values of the StateRatio table will be used instead. Valid Range
</span><br><span style="color: hsl(120, 100%, 40%);">+ of each entry is 0 to 0x7F
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 StateRatioMax16[16];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0856 - Platform Power Pmax
</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0-1024 Watts. Value of 800 = 100W
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PsysPmax;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0
</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl0Irtl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1
</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl1Irtl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2
</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl2Irtl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3
</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl3Irtl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4
</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl4Irtl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5
</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl5Irtl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0864 - Package Long duration turbo mode power limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PowerLimit1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0868 - Package Short duration turbo mode power limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PowerLimit2Power;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x086C - Package PL3 power limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PowerLimit3;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0870 - Package PL4 power limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 1023875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PowerLimit4;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0874 - Tcc Offset Time Window for RATL
</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 1023875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TccOffsetTimeWindowForRatl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1
</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom1PowerLimit1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x087C - Long term Power Limit value for custom cTDP level 1
</span><br><span style="color: hsl(120, 100%, 40%);">+ Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom1PowerLimit2;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2
</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom2PowerLimit1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2
</span><br><span style="color: hsl(120, 100%, 40%);">+ Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom2PowerLimit2;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3
</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom3PowerLimit1;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x088C - Long term Power Limit value for custom cTDP level 3
</span><br><span style="color: hsl(120, 100%, 40%);">+ Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom3PowerLimit2;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0890 - Platform PL1 power
</span><br><span style="color: hsl(120, 100%, 40%);">+ Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PsysPowerLimit1Power;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0894 - Platform PL2 power
</span><br><span style="color: hsl(120, 100%, 40%);">+ Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 to 4095875 in Step size of 125
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PsysPowerLimit2Power;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0898 - Set Three Strike Counter Disable
</span><br><span style="color: hsl(120, 100%, 40%);">+ False (default): Three Strike counter will be incremented and True: Prevents Three
</span><br><span style="color: hsl(120, 100%, 40%);">+ Strike counter from incrementing; <b>0: False</b>; 1: True.
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: False, 1: True
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThreeStrikeCounterDisable;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
</span><br><span style="color: hsl(120, 100%, 40%);">+ Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HwpInterruptControl;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089A - 5-Core Ratio Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0:0xFF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FiveCoreRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089B - 6-Core Ratio Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0:0xFF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SixCoreRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089C - 7-Core Ratio Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0:0xFF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SevenCoreRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089D - 8-Core Ratio Limit
</span><br><span style="color: hsl(120, 100%, 40%);">+ 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core
</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0:0xFF
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EightCoreRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089E - Intel Turbo Boost Max Technology 3.0
</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableItbm;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver
</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableItbmDriver;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C1StateAutoDemotion;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C1StateUnDemotion;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A2 - CpuWakeUpTimer
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased
</span><br><span style="color: hsl(120, 100%, 40%);">+ to 180 seconds. 0: Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CpuWakeUpTimer;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A3 - Minimum Ring ratio limit override
</span><br><span style="color: hsl(120, 100%, 40%);">+ Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
</span><br><span style="color: hsl(120, 100%, 40%);">+ ratio limit
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MinRingRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A4 - Minimum Ring ratio limit override
</span><br><span style="color: hsl(120, 100%, 40%);">+ Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
</span><br><span style="color: hsl(120, 100%, 40%);">+ ratio limit
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MaxRingRatioLimit;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C3StateAutoDemotion;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C3StateUnDemotion;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A7 - ReservedCpuPostMemTest
</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for CPU Post-Mem Test
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedCpuPostMemTest[19];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BA - SgxSinitDataFromTpm
</span><br><span style="color: hsl(120, 100%, 40%);">+ SgxSinitDataFromTpm default values
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SgxSinitDataFromTpm;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BB - End of Post message
</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
</span><br><span style="color: hsl(120, 100%, 40%);">+ EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EndOfPostMessage;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BC - D0I3 Setting for HECI Disable
</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
</span><br><span style="color: hsl(120, 100%, 40%);">+ HECI devices
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableD0I3SettingForHeci;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BD - HD Audio Reset Wait Timer
</span><br><span style="color: hsl(120, 100%, 40%);">+ The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchHdaResetWaitTimer;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BF - Enable LOCKDOWN SMI
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLockDownGlobalSmi;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface
</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLockDownBiosInterface;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C1 - Unlock all GPIO pads
</span><br><span style="color: hsl(120, 100%, 40%);">+ Force all GPIO pads to be unlocked for debug purpose.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUnlockGpioPads;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C2 - PCH Unlock SBI access
</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSbiUnlock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C3 - PCH Unlock SideBand access
</span><br><span style="color: hsl(120, 100%, 40%);">+ The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
</span><br><span style="color: hsl(120, 100%, 40%);">+ 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSbAccessUnlock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Max Snoop Latency.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpLtrMaxSnoopLatency[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Max Non-Snoop Latency.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpLtrMaxNoSnoopLatency[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0924 - PCIE RP Snoop Latency Override Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Snoop Latency Override Mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSnoopLatencyOverrideMode[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0954 - PCIE RP Snoop Latency Override Value
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Snoop Latency Override Value.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpSnoopLatencyOverrideValue[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value
</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x09E4 - PCIE RP Slot Power Limit Scale
</span><br><span style="color: hsl(120, 100%, 40%);">+ Specifies scale used for slot power limit value. Leave as 0 to set to default.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSlotPowerLimitScale[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x09FC - PCIE RP Slot Power Limit Value
</span><br><span style="color: hsl(120, 100%, 40%);">+ Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpSlotPowerLimitValue[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset
</span><br><span style="color: hsl(120, 100%, 40%);">+ Used during Gen3 Link Equalization. Used for all lanes. Default is 5.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpUptp[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset
</span><br><span style="color: hsl(120, 100%, 40%);">+ Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpDptp[24];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A5C - PCIE RP Enable Port8xh Decode
</span><br><span style="color: hsl(120, 100%, 40%);">+ This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieEnablePort8xhDecode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A5D - PCIE Port8xh Decode Port Index
</span><br><span style="color: hsl(120, 100%, 40%);">+ The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPciePort8xhDecodePortIndex;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A5E - PCH Energy Reporting
</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable/Enable PCH to CPU energy report feature.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmDisableEnergyReport;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A5F - PCH Sata Test Mode
</span><br><span style="color: hsl(120, 100%, 40%);">+ Allow entrance to the PCH SATA test modes.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataTestMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable
</span><br><span style="color: hsl(120, 100%, 40%);">+ If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
</span><br><span style="color: hsl(120, 100%, 40%);">+ that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchXhciOcLock;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A61
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace24[17];
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A72 - Skip POSTBOOT SAI
</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipPostBootSai;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A73 - Mctp Broadcast Cycle
</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MctpBroadcastCycle;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A74
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsTestUpd[12];
</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_S_TEST_CONFIG;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S UPD Configuration
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0000
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_UPD_HEADER FspUpdHeader;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_CONFIG FspsConfig;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AD
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_TEST_CONFIG FspsTestConfig;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A80
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 UpdTerminator;
</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPS_UPD;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28286">change 28286</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28286"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I656da83e9042642576b785643e423ba47da8dd73 </div>
<div style="display:none"> Gerrit-Change-Number: 28286 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>