<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28289">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">util/msrtool: Fix typo<br><br>Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M util/msrtool/intel_atom.c<br>M util/msrtool/intel_core2_later.c<br>M util/msrtool/intel_nehalem.c<br>3 files changed, 22 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/28289/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c</span><br><span>index f2df5ae..489e0a0 100644</span><br><span>--- a/util/msrtool/intel_atom.c</span><br><span>+++ b/util/msrtool/intel_atom.c</span><br><span>@@ -278,7 +278,7 @@</span><br><span>            }},</span><br><span>          { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {</span><br><span>                    /* This bit enables a system executive to use</span><br><span style="color: hsl(0, 100%, 40%);">-                    * VMX in conjuction with SMX to support Intel</span><br><span style="color: hsl(120, 100%, 40%);">+                         * VMX in conjunction with SMX to support Intel</span><br><span>                       * Trusted Execution Technology.</span><br><span>                      */</span><br><span>                  { MSR1(0), "VMX inside of SMX operation disabled" },</span><br><span>@@ -797,9 +797,9 @@</span><br><span>                 /* if CPUID.0AH EAX[7:0] > 2 */</span><br><span>           { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {</span><br><span>                    { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {</span><br><span>@@ -820,9 +820,9 @@</span><br><span>           /* if CPUID.0AH: EAX[7:0] > 2 */</span><br><span>          { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {</span><br><span>                     { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {</span><br><span>@@ -843,9 +843,9 @@</span><br><span>           /* if CPUID.0AH: EAX[7:0] > 2 */</span><br><span>          { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {</span><br><span>                     { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {</span><br><span>diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c</span><br><span>index 4bb0097..95e8e91 100644</span><br><span>--- a/util/msrtool/intel_core2_later.c</span><br><span>+++ b/util/msrtool/intel_core2_later.c</span><br><span>@@ -232,7 +232,7 @@</span><br><span>              }},</span><br><span>          { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {</span><br><span>                    /* This bit enables a system executive to use</span><br><span style="color: hsl(0, 100%, 40%);">-                    * VMX in conjuction with SMX to support Intel</span><br><span style="color: hsl(120, 100%, 40%);">+                         * VMX in conjunction with SMX to support Intel</span><br><span>                       * Trusted Execution Technology.</span><br><span>                      */</span><br><span>                  { MSR1(0), "VMX inside of SMX operation disabled" },</span><br><span>@@ -821,9 +821,9 @@</span><br><span>                 /* if CPUID.0AH EAX[7:0] > 2 */</span><br><span>           { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {</span><br><span>                    { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {</span><br><span>@@ -844,9 +844,9 @@</span><br><span>           /* if CPUID.0AH: EAX[7:0] > 2 */</span><br><span>          { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {</span><br><span>                     { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {</span><br><span>@@ -867,9 +867,9 @@</span><br><span>           /* if CPUID.0AH: EAX[7:0] > 2 */</span><br><span>          { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {</span><br><span>                     { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {</span><br><span>diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c</span><br><span>index 11acdd8..726ad0a 100644</span><br><span>--- a/util/msrtool/intel_nehalem.c</span><br><span>+++ b/util/msrtool/intel_nehalem.c</span><br><span>@@ -307,7 +307,7 @@</span><br><span>              }},</span><br><span>          { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {</span><br><span>                    /* This bit enables a system executive to use</span><br><span style="color: hsl(0, 100%, 40%);">-                    * VMX in conjuction with SMX to support Intel</span><br><span style="color: hsl(120, 100%, 40%);">+                         * VMX in conjunction with SMX to support Intel</span><br><span>                       * Trusted Execution Technology.</span><br><span>                      */</span><br><span>                  { MSR1(0), "VMX inside of SMX operation disabled" },</span><br><span>@@ -1109,7 +1109,7 @@</span><br><span>               /* Whole package bit */</span><br><span>              { 1, 1, "C1E Enable", "R/W", PRESENT_BIN, {</span><br><span>                      { MSR1(0), "Nothing" },</span><br><span style="color: hsl(0, 100%, 40%);">-                       { MSR1(1), "CPU switch to the Minimum Enhaced Intel \</span><br><span style="color: hsl(120, 100%, 40%);">+                    { MSR1(1), "CPU switch to the Minimum Enhanced Intel \</span><br><span>                          SpeedStep Technology operating point when all \</span><br><span>                              execution cores enter MWAIT (C1)" },</span><br><span>                    { BITVAL_EOT }</span><br><span>@@ -1373,9 +1373,9 @@</span><br><span>               /* if CPUID.0AH EAX[7:0] > 2 */</span><br><span>           { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {</span><br><span>                    { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {</span><br><span>@@ -1396,9 +1396,9 @@</span><br><span>                 /* if CPUID.0AH: EAX[7:0] > 2 */</span><br><span>          { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {</span><br><span>                     { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {</span><br><span>@@ -1419,9 +1419,9 @@</span><br><span>                 /* if CPUID.0AH: EAX[7:0] > 2 */</span><br><span>          { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {</span><br><span>                     { MSR1(0), "Counter only increments the associated event \</span><br><span style="color: hsl(0, 100%, 40%);">-                         conditions occuring in the logical processor which programmed the MSR" },</span><br><span style="color: hsl(120, 100%, 40%);">+                                conditions occurring in the logical processor which programmed the MSR" },</span><br><span>                      { MSR1(1), "Counting the associated event conditions \</span><br><span style="color: hsl(0, 100%, 40%);">-                             occuring across all logical processors sharing a processor core" },</span><br><span style="color: hsl(120, 100%, 40%);">+                              occurring across all logical processors sharing a processor core" },</span><br><span>                    { BITVAL_EOT }</span><br><span>               }},</span><br><span>          { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28289">change 28289</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28289"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5 </div>
<div style="display:none"> Gerrit-Change-Number: 28289 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>