<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28298">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/amd/pi/00670F00: Remove IDS headers<br><br>Only Ids.h had definitions still in use, and they were removed or moved to<br>AGESA.h. Now Ids.h and IdsLib.h can be safely removed.<br><br>BUG=b:112885948<br>TEST=Build grunt<br><br>Change-Id: If77250c9953d9eda00496e934b689290d0de1511<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>D src/vendorcode/amd/pi/00670F00/Include/Ids.h<br>D src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h<br>D src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h<br>M src/vendorcode/amd/pi/00670F00/agesa_headers.h<br>4 files changed, 0 insertions(+), 1,659 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/28298/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/amd/pi/00670F00/Include/Ids.h b/src/vendorcode/amd/pi/00670F00/Include/Ids.h</span><br><span>deleted file mode 100644</span><br><span>index cc1a2b9..0000000</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Include/Ids.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,1443 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/* $NoKeywords:$ */</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @file</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * AMD IDS Routines</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Contains AMD AGESA Integrated Debug Macros</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @xrefitem bom "File Content Label" "Release Content"</span><br><span style="color: hsl(0, 100%, 40%);">- * @e project: AGESA</span><br><span style="color: hsl(0, 100%, 40%);">- * @e sub-project: IDS</span><br><span style="color: hsl(0, 100%, 40%);">- * @e \$Revision$ @e \$Date$</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- /*****************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * All rights reserved.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Redistribution and use in source and binary forms, with or without</span><br><span style="color: hsl(0, 100%, 40%);">- * modification, are permitted provided that the following conditions are met:</span><br><span style="color: hsl(0, 100%, 40%);">- * * Redistributions of source code must retain the above copyright</span><br><span style="color: hsl(0, 100%, 40%);">- * notice, this list of conditions and the following disclaimer.</span><br><span style="color: hsl(0, 100%, 40%);">- * * Redistributions in binary form must reproduce the above copyright</span><br><span style="color: hsl(0, 100%, 40%);">- * notice, this list of conditions and the following disclaimer in the</span><br><span style="color: hsl(0, 100%, 40%);">- * documentation and/or other materials provided with the distribution.</span><br><span style="color: hsl(0, 100%, 40%);">- * * Neither the name of Advanced Micro Devices, Inc. nor the names of</span><br><span style="color: hsl(0, 100%, 40%);">- * its contributors may be used to endorse or promote products derived</span><br><span style="color: hsl(0, 100%, 40%);">- * from this software without specific prior written permission.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND</span><br><span style="color: hsl(0, 100%, 40%);">- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED</span><br><span style="color: hsl(0, 100%, 40%);">- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE</span><br><span style="color: hsl(0, 100%, 40%);">- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY</span><br><span style="color: hsl(0, 100%, 40%);">- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span><br><span style="color: hsl(0, 100%, 40%);">- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;</span><br><span style="color: hsl(0, 100%, 40%);">- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND</span><br><span style="color: hsl(0, 100%, 40%);">- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT</span><br><span style="color: hsl(0, 100%, 40%);">- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS</span><br><span style="color: hsl(0, 100%, 40%);">- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <check_for_wrapper.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Macros to aid debugging */</span><br><span style="color: hsl(0, 100%, 40%);">- /* These definitions expand to zero (0) bytes of code when disabled */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _IDS_H_</span><br><span style="color: hsl(0, 100%, 40%);">-#define _IDS_H_</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#undef FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#undef TRUE</span><br><span style="color: hsl(0, 100%, 40%);">-#define FALSE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRUE 1</span><br><span style="color: hsl(0, 100%, 40%);">-// Proto type for optionsids.h</span><br><span style="color: hsl(0, 100%, 40%);">-typedef UINT32 IDS_STATUS; ///< Status of IDS function.</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_SUCCESS ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful.</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_STRINGIZE(a) #a ///< for define stringize macro</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDS_DEADLOOP</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * IDS Option Hook Points</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * These are the values to indicate hook point in AGESA for IDS Options.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-typedef enum { //vv- for debug reference only</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.</span><br><span style="color: hsl(0, 100%, 40%);">- ///< IDS Object is initialized.</span><br><span style="color: hsl(0, 100%, 40%);">- ///< Override CPU Core Leveling Mode.</span><br><span style="color: hsl(0, 100%, 40%);">- ///< Set P-State in Post</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.</span><br><span style="color: hsl(0, 100%, 40%);">- ///< It will be used to control the following tables.</span><br><span style="color: hsl(0, 100%, 40%);">- ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)</span><br><span style="color: hsl(0, 100%, 40%);">- ///< ACPI WHEA Table</span><br><span style="color: hsl(0, 100%, 40%);">- ///< DMI Table</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.</span><br><span style="color: hsl(0, 100%, 40%);">- ///< Control Interleaving and DRAM memory hole</span><br><span style="color: hsl(0, 100%, 40%);">- ///< Override the setting of ECC Control</span><br><span style="color: hsl(0, 100%, 40%);">- ///< Override the setting of Online Spare Rank</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_RTB_BEFORE, ///< 18 Option Hook Point before AGESA function AMD_INIT_RTB.</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_RTB_AFTER, ///< 19 Option Hook Point after AGESA function AMD_INIT_RTB.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // All the above timing point is used by BVM, their value should never be changed</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_DRAM_TABLE, ///< 40 Generate override table for Dram Timing</span><br><span style="color: hsl(0, 100%, 40%);">- ///< Dram Controller, Drive Strength and DQS Timing</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GET_DRAM_TABLE, ///< 41 Generate override table for Dram Timing</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GANGING_MODE, ///< 42 override Memory Mode Unganged</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_POWERDOWN_MODE, ///< 43 override Power Down Mode</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BURST_LENGTH32, ///< 44 override Burst Length32</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ALL_MEMORY_CLOCK, ///< 45 override All Memory Clks Enable</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ECC, ///< 46 override ECC parameter</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ECCSYMBOLSIZE, ///< 47 override ECC symbol size</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CPU_Early_Override, ///< 48 override CPU early parameter</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CACHE_FLUSH_HLT, ///< 49 override Cache Flush Hlt</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CHANNEL_INTERLEAVE, ///< 4a override Channel Interleave</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_ERROR_RECOVERY, ///< 4b override memory error recovery</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_RETRAIN_TIMES, ///< 4c override memory retrain times</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_SIZE_OVERLAY, ///< 4d Override the syslimit</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CHECK_NEGATIVE_WL, ///< 4e Check for negative write leveling result</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_DLL_SHUT_DOWN, ///< 4f Check for Dll Shut Down</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_POR_MEM_FREQ, ///< 50 Entry to enable/disable MemClk frequency enforcement</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PHY_DLL_STANDBY_CTRL, ///< 51 Enable/Disable Phy DLL standby feature</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PLATFORMCFG_OVERRIDE, ///< 52 Hook for Override PlatformConfig structure</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_LOADCARD_ERROR_RECOVERY, ///< 53 Special error handling for load card support</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_IGNORE_ERROR, ///< 54 Ignore error and do not do fatal exit in memory</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_SMU_SERVICE_CONFIG, ///< 55 Config GNB SMU service</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_ORBDYNAMIC_WAKE, ///< 56 config GNB dynamic wake</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 57 override ids gnb platform config</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_LCLK_DPM_EN, ///< 58 override GNB LCLK DPM configuration</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_LCLK_DEEP_SLEEP, ///< 59 override GNB LCLK DPM deep sleep</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_CLOCK_GATING, ///< 5a Override GNB Clock gating config</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_NB_PSTATE_DIDVID, ///< 5b Override NB P-state settings</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CPB_CTRL, ///< 5c Config the Core peformance boost feature</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_HTC_CTRL, ///< 5d Hook for Hardware Thermal Control</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CC6_WORKAROUND, ///< 5e Hook for skip CC6 work around</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_MR0, ///< 5f Hook for override Memory Mr0 register</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_TRAP_TABLE, ///< 60 Hook for add IDS register table to the loop</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_NBBUFFERALLOCATIONATEARLY, ///< 61 Hook for override North bridge bufer allocation</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_S3_SPECIAL, ///< 62 Hook to bypass S3 special functions</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_SET_PCI_REGISTER_ENTRY, ///< 63 Hook to SetRegisterForPciEntry</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ERRATUM463_WORKAROUND, ///< 64 Hook to Erratum 463 workaround</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_MEMCLR, ///< 65 Hook before set Memclr bit</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_OVERRIDE_IO_CSTATE, ///< 66 Hook for override io C-state setting</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_NBPSDIS_OVERRIDE, ///< 67 Hook for override NB pstate disable setting</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_NBPS_REG_OVERRIDE, ///< 68 Hook for override Memory NBps reg</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_PHY_POWER_SAVING, ///< 69 Hook to bypass DRAM Phy power savings</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CST_CREATE, ///< 6a Hook for create _CST</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CST_SIZE, ///< 6b Hook for get _CST size</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ENFORCE_VDDIO, ///< 6c Hook to override VDDIO</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_STRETCH_FREQUENCY_LIMIT, ///< 6d Hook for enforcing memory stretch frequency limit</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_INIT_MEM_REG_TABLE, ///< 6e Hook for init memory register table</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_SKIP_FUSED_MAX_RATE, ///< 6f Hook to skip fused max rate cap</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FCH_INIT_AT_RESET, ///< 70 Hook for FCH reset parameter</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FCH_INIT_AT_ENV, ///< 71 Hook for FCH ENV parameter</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ENFORCE_PLAT_TABLES, ///< 72 Hook to enforce platform specific tables</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_NBPS_MIN_FREQ, ///< 73 Hook for override MIN nb ps freq</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_FORCE_CABLESAFE, ///< 74 Hook for override Force Cable Safe</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_SKIP_PM_TRANSITION_STEP, ///< 75 Hook for provide IDS ability to skip this PM step</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PROPERTY, ///< 76 Hook for GNB Property</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PCIE_POWER_GATING, ///< 77 Hook for GNB PCIe Power Gating</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_DYN_DRAM_TERM, ///< 78 Hook for Override Dynamic Dram Term</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_DRAM_TERM, ///< 79 Hook for Override Dram Term</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_ALTVDDNB, ///< 7a Hook for Override AltVddNB</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_UCODE, ///< 7b Enable or Disable microcode patching</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FAM_REG_GMMX, ///< 7c GMMX register access</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEMORY_POWER_POLICY, ///< 7d Memory power policy</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 7e Hook for enforcing memory stretch frequency limit</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CPU_FEAT, ///< 7f Hook for runtime force cpu feature disable</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_AFTER_DCT_PHY_ACCESS, ///< 80 Hook for DctAccessDone check</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FORCE_PHY_TO_M0, ///< 81 Hook to bypass M0 enforcement</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PMM_SWTJOFFSET, ///< 82 Hook to GNBSWTJOFFSET</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_LOCK_DRAM_CFG, ///< 83 Hook to BFLockDramCfg</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_GEN2_INIT, ///< 84 Hook to Before Gen2 Init</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_GPP_TRAINING, ///< 85 Hook to Before Gpp training</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_RECONFIGURATION, ///< 86 Hook to Before Reconfiguration</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_GEN3_INIT, ///< 87 Hook to Before Gen3 Init</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_POWER_GATING, ///< 88 Hook to Before Power Gating</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_AFTER_EARLY_INIT_ONCORE, ///< 89 Hook to after EarlyInit On Core</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PCIE_PORT_REMAP, ///< 8a Hook to change mapping of PCIe devices</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ECC_CONTROL, ///< 8b Enable/Disable ECC feature</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PCIE_PHY_ISOLATION, ///< 8c Enable/Disable PCIE PHY ISOLATION</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_AFTER_RESTORING_PCI_REG, ///< 8d Hook after restoring PCI register during S3 resume</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MSR_ACCESS_OVERRIDE, ///< 8e Hook to disable MSR access</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_REPORT_SMU_FW_VERSION, ///< 8f Hook to report SMU firmware version</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_LOAD_SAMU_PATCH, ///< 90 Hook to Load SAMU patch</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_DLLSTAGGERDLY_OVERRIDE, ///< 91 Hook to skip Dll Stagger Delay</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CSAMPLE_TIMER, ///< 92 Hook to override CSampleTimer</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_PIPE_THROTTLE, ///< 93 Hook to override PipeThrottle</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PMM_NATIVEGEN1PLL, ///< 94 Enable/Disable Native Gen1 PLL</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_PLAT_TABLES, ///< 95 Hook before processing platform specific tables</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PCIE_MASTERPLL_SELECTION, ///< 96 Hook to override PCIe Master PLL selection</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_PCIE_PHYLANE_CONFIG, ///< 97 Hook to override PCIe PhyLane configuration</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_DSM_LP_SELECTION, ///< 98 Set Dsm low power mode</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_EQUAL_PRESET, ///< 99 Set equalization preset</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_GEN1_LOOPBACK, ///< 9a Override Gen 1 loopback mode</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_SMU_SERVICE_MASK, ///< 9b Override SMU service enablement mask</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BEFORE_HT_MEM_MAP, ///< 9c Hook before mapping memory address space among DCTs</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_GEN3_SETTINGS_OVERRIDE, ///< 9d Hook to override Gen3 Adapt PI Offset Bypass Enable</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_TARGET_TDP, ///< 9e Hook to override Target TDP</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_GNB_SMU_PORT80_PARAMS, ///< 9f Hook to override gnb smu port80 values</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_CPU_OVERRIDE_REG_AFTER_AP_LAUNCH, ///< a0 Hook to override registers after AP lauch</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_AFTER_FEAT_MID_INIT, ///< a1 Hook to override feature setting after cpuMidInit</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_MCLK_ABOVE_NCLK, ///< a2 Hook to bypass system bandwidth for memory clock</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ALL_MEMORY_CKE, ///< a3 override All Memory CKE</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_ALL_MEMORY_CS, ///< a4 override All Memory CS</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_NPST, ///< a5 cTDP NbPstate Selection Table</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_MRL_RETRAIN_TIMES, ///< a6 override memory MRL retrain times</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_AFTER_DQS_TRAINING, ///< a7 override any settings after DQS training</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_OVERRIDE_DIMM_MASK, ///< a8 override DimmMask for S3 data blob creation</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_BYPASS_S3_REGISTERS, ///< a9 bypass restoring certain registers</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_RTTNOM, ///< aa Hook for Override RttNom</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_RTTWR, ///< ab Hook for Override RttWr</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_RTTPARK, ///< ac Hook for Override RttPark</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_ADDR_CMD_TMG, ///< ad Address command timing</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_MR6_VREF_DQ, ///< ae MR6 VRefDQ</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_MEM_PMU_RETRAIN_TIMES, ///< af override memory PMU retrain times</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_OPTION_END ///< B0 End of IDS option</span><br><span style="color: hsl(0, 100%, 40%);">-} AGESA_IDS_OPTION;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include "OptionsIds.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "Filecode.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "IdsPerf.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Initialize IDS controls */</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_IDS_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_IDS_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_CONTROL_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_CONTROL_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_CONTROL_NV_TO_CMOS</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_CONTROL_NV_TO_CMOS FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_TRACING_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_TRACE_USER_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACE_USER_OPTIONS TRUE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_PERF_ANALYSIS</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_PERF_ANALYSIS FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_HEAP_CHECKING</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_HEAP_CHECKING FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_ASSERT_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_ASSERT_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_DEBUG_CODE_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_DEBUG_CODE_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_IDT_EXCEPTION_TRAP</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_IDT_EXCEPTION_TRAP FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_C_OPTIMIZATION_DISABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_TRACING_CONSOLE_HDTOUT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_HDTOUT TRUE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_TRACING_CONSOLE_SERIALPORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_TRACING_CONSOLE_REDIRECT_IO</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDSOPT_TRACING_CONSOLE_RAM</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_RAM FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_IDS_ENABLED == FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_CONTROL_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_PERF_ANALYSIS</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_HEAP_CHECKING</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_ASSERT_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_DEBUG_CODE_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACE_USER_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_CONSOLE_HDTOUT</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_CONSOLE_SERIALPORT</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_CONSOLE_RAM</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_CONTROL_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_PERF_ANALYSIS FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_HEAP_CHECKING FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_ASSERT_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_DEBUG_CODE_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACE_USER_OPTIONS FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_RAM FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//Disable when master token Tracing is set to FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#if (IDSOPT_TRACING_ENABLED == FALSE) || (defined (IDSOPT_CUSTOMIZE_TRACING_SERVICE))</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_CONSOLE_HDTOUT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_CONSOLE_SERIALPORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_CONSOLE_RAM</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_CONSOLE_RAM FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//Disable Tracing if all support HW layer set to FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#if ((IDSOPT_TRACING_CONSOLE_HDTOUT == FALSE) && (IDSOPT_TRACING_CONSOLE_SERIALPORT == FALSE) && (IDSOPT_TRACING_CONSOLE_REDIRECT_IO == FALSE) && (IDSOPT_TRACING_CONSOLE_RAM == FALSE))</span><br><span style="color: hsl(0, 100%, 40%);">- #ifndef IDSOPT_CUSTOMIZE_TRACING_SERVICE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDSOPT_TRACING_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDSOPT_TRACING_ENABLED FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Make a Progress Report to the User.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This Macro is always enabled. The default action is to write the TestPoint value</span><br><span style="color: hsl(0, 100%, 40%);">- * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.</span><br><span style="color: hsl(0, 100%, 40%);">- * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port</span><br><span style="color: hsl(0, 100%, 40%);">- * in OptionsIds.h in their build tip.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] TestPoint The value for display indicating progress</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDS_DEBUG_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_PORT 0x80</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDS_DEBUG_PORT > 0xFFFFul</span><br><span style="color: hsl(0, 100%, 40%);">- #error "Invalid debug port defined. IDS_DEBUG_PORT address must not be larger than 16 bits."</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDS_DEBUG_PORT_SIZE_IN_BYTES</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_PORT_SIZE_IN_BYTES 4</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDS_DEBUG_PORT_SIZE_IN_BYTES == 1</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth8</span><br><span style="color: hsl(0, 100%, 40%);">- #ifndef IDS_DEBUG_TP_PREFIX</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_TP_PREFIX 0x00ul</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDS_DEBUG_TP_PREFIX != 0</span><br><span style="color: hsl(0, 100%, 40%);">- #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES."</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDS_DEBUG_PORT_SIZE_IN_BYTES == 2</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth16</span><br><span style="color: hsl(0, 100%, 40%);">- #ifndef IDS_DEBUG_TP_PREFIX</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_TP_PREFIX 0xA0ul</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDS_DEBUG_TP_PREFIX > 0xFFul</span><br><span style="color: hsl(0, 100%, 40%);">- #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES."</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDS_DEBUG_PORT_SIZE_IN_BYTES == 4</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth32</span><br><span style="color: hsl(0, 100%, 40%);">- #ifndef IDS_DEBUG_TP_PREFIX</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_TP_PREFIX 0xA9E5A0ul</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDS_DEBUG_TP_PREFIX > 0xFFFFFFul</span><br><span style="color: hsl(0, 100%, 40%);">- #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES."</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #error "Invalid debug port size defined. Acceptable values of IDS_DEBUG_PORT_SIZE_IN_BYTES are 1, 2, or 4."</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if (IDS_DEBUG_PORT & (IDS_DEBUG_PORT_SIZE_IN_BYTES - 1)) != 0</span><br><span style="color: hsl(0, 100%, 40%);">- #error "IDS_DEBUG_PORT must be aligned on IDS_DEBUG_PORT_SIZE_IN_BYTES boundary."</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @def STOP_HERE</span><br><span style="color: hsl(0, 100%, 40%);">- * (macro) - Causes program to halt. This is @b only for use during active debugging .</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Causes the program to halt and display the file number of the source of the</span><br><span style="color: hsl(0, 100%, 40%);">- * halt (displayed in decimal).</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_IDS_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef STOP_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef STOP_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \</span><br><span style="color: hsl(0, 100%, 40%);">- ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \</span><br><span style="color: hsl(0, 100%, 40%);">- (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))</span><br><span style="color: hsl(0, 100%, 40%);">- #define STOP_HERE IdsErrorStop (STOP_CODE);</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @def ASSERT</span><br><span style="color: hsl(0, 100%, 40%);">- * Test an assertion that the given statement is True.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * The statement is evaluated to a boolean value. If the statement is True,</span><br><span style="color: hsl(0, 100%, 40%);">- * then no action is taken (no error). If the statement is False, a error stop</span><br><span style="color: hsl(0, 100%, 40%);">- * is generated to halt the program. Used for testing for fatal errors that</span><br><span style="color: hsl(0, 100%, 40%);">- * must be resolved before production. This is used to do parameter checks,</span><br><span style="color: hsl(0, 100%, 40%);">- * bounds checking, range checks and 'sanity' checks.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] conditional Assert that evaluating this conditional results in TRUE.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef ASSERT</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDSOPT_ASSERT_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef STOP_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef STOP_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \</span><br><span style="color: hsl(0, 100%, 40%);">- ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \</span><br><span style="color: hsl(0, 100%, 40%);">- (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #define ASSERT(conditional)</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_CAR_CORRUPTION_CHECK(StdHeader) IdsCarCorruptionCheck(StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_CAR_CORRUPTION_CHECK(StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @def DEBUG_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef DEBUG_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDSOPT_DEBUG_CODE_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #define DEBUG_CODE(Code) Code</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #define DEBUG_CODE(Code)</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///give the extended Macro default value</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __IDS_EXTENDED__</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_TRACE_DEFAULT (0)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_INITIAL_F15_CZ_PM_STEP</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_INITIAL_F15_ST_PM_STEP</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_F15_CZ_PM_CUSTOM_STEP</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_F15_ST_PM_CUSTOM_STEP</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXTENDED_HEAP_SIZE 0</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXT_INCLUDE_F15(file)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXT_INCLUDE(file)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_PAD_4K</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXTENDED_CODE(code)</span><br><span style="color: hsl(0, 100%, 40%);">- #define SMU_FIRMWARE_PADS_1K</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDS_NUM_NV_ITEM</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_CMOS_INDEX_PORT 0x70</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_CMOS_DATA_PORT 0x71</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_CMOS_REGION_START 0x20</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_CMOS_REGION_END 0x7F</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_CONTROL_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \</span><br><span style="color: hsl(0, 100%, 40%);">- AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) \</span><br><span style="color: hsl(0, 100%, 40%);">- IdsOptionCallout ((CallOutId), (DataPtr), (StdHeader))</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_AP_GET_NV_FROM_CMOS</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_AP_GET_NV_FROM_CMOS(x) AmdIdsApGetNvFromCmos(x)</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDS_OPT_CMOS_INDEX_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_CMOS_INDEX_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDS_OPT_CMOS_DATA_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_CMOS_DATA_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDS_OPT_CMOS_REGION_START</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_CMOS_REGION_START</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDS_OPT_CMOS_REGION_END</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_CMOS_REGION_END</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Macro to add a *skip* hook for IDS options</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * The default minimal action is to do nothing and there is no any code to increase.</span><br><span style="color: hsl(0, 100%, 40%);">- * For debug environments, IDS dispatcher function will be called to perform</span><br><span style="color: hsl(0, 100%, 40%);">- * the detailed action and to skip AGESA code if necessary.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] IdsOption IDS Option ID for this hook point</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in, out] DataPtr Data Pointer to override</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_CONTROL_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \</span><br><span style="color: hsl(0, 100%, 40%);">- if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Macro to add a heap manager routine</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * when memory is allocated the heap manager actually allocates two extra dwords of data,</span><br><span style="color: hsl(0, 100%, 40%);">- * one dword buffer before the actual memory, and one dword afterwards.</span><br><span style="color: hsl(0, 100%, 40%);">- * a complete heap walk and check to be performed at any time.</span><br><span style="color: hsl(0, 100%, 40%);">- * it would ASSERT if the heap is corrupt</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// Heap debug feature</span><br><span style="color: hsl(0, 100%, 40%);">-#define SENTINEL_BEFORE_VALUE 0x64616548ul // "Head"</span><br><span style="color: hsl(0, 100%, 40%);">-#define SENTINEL_AFTER_VALUE 0x6C696154ul // "Tail"</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_IDS_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDSOPT_HEAP_CHECKING == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #define SIZE_OF_SENTINEL 4</span><br><span style="color: hsl(0, 100%, 40%);">- #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail")</span><br><span style="color: hsl(0, 100%, 40%);">- #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);</span><br><span style="color: hsl(0, 100%, 40%);">- #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);</span><br><span style="color: hsl(0, 100%, 40%);">- #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader)</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #define SIZE_OF_SENTINEL 0</span><br><span style="color: hsl(0, 100%, 40%);">- #define NUM_OF_SENTINEL 0</span><br><span style="color: hsl(0, 100%, 40%);">- #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)</span><br><span style="color: hsl(0, 100%, 40%);">- #define SET_SENTINEL_AFTER(NodePtr)</span><br><span style="color: hsl(0, 100%, 40%);">- #define Heap_Check(stdheader)</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define SIZE_OF_SENTINEL 0</span><br><span style="color: hsl(0, 100%, 40%);">- #define NUM_OF_SENTINEL 0</span><br><span style="color: hsl(0, 100%, 40%);">- #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)</span><br><span style="color: hsl(0, 100%, 40%);">- #define SET_SENTINEL_AFTER(NodePtr)</span><br><span style="color: hsl(0, 100%, 40%);">- #define Heap_Check(stdheader)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Macro to add IDT for debugging exception.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * A debug feature. Adding a 'jmp $' into every exception handler.</span><br><span style="color: hsl(0, 100%, 40%);">- * So debugger could use HDT to skip 'jmp $' and execute the iret,</span><br><span style="color: hsl(0, 100%, 40%);">- * then they could find which instruction cause the exception.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] FunctionId IDS Function ID for this hook point</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in, out] DataPtr Data Pointer to override</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_IDS_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) IdsExceptionTrap (FunctionId, DataPtr, StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- //Note a is from 0 to 63</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)</span><br><span style="color: hsl(0, 100%, 40%);">-//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly</span><br><span style="color: hsl(0, 100%, 40%);">-//Memory Masks</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_SETREG DEBUG_PRINT_SHIFT (0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_GETREG DEBUG_PRINT_SHIFT (1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_FLOW DEBUG_PRINT_SHIFT (2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_STATUS DEBUG_PRINT_SHIFT (3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_PMU DEBUG_PRINT_SHIFT (5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//CPU Masks</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE DEBUG_PRINT_SHIFT (10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//GNB Masks</span><br><span style="color: hsl(0, 100%, 40%);">-#define GNB_TRACE DEBUG_PRINT_SHIFT (20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIE_MISC DEBUG_PRINT_SHIFT (21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_MISC DEBUG_PRINT_SHIFT (25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GFX_MISC DEBUG_PRINT_SHIFT (27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//Topology Masks</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE DEBUG_PRINT_SHIFT (30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//FCH Masks</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE DEBUG_PRINT_SHIFT (40)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//Other Masks</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)</span><br><span style="color: hsl(0, 100%, 40%);">-#define EVENT_LOG DEBUG_PRINT_SHIFT (51)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//Ids Masks</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_TRACE DEBUG_PRINT_SHIFT (53)</span><br><span style="color: hsl(0, 100%, 40%);">-#define BVM_TRACE DEBUG_PRINT_SHIFT (54)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//S3</span><br><span style="color: hsl(0, 100%, 40%);">-#define S3_TRACE DEBUG_PRINT_SHIFT (57)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//Library function to read/write PCI/MSR registers</span><br><span style="color: hsl(0, 100%, 40%);">-#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//AGESA test points</span><br><span style="color: hsl(0, 100%, 40%);">-#define TEST_POINT DEBUG_PRINT_SHIFT (60)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//Reserved for platform log</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLAT_RSV1 DEBUG_PRINT_SHIFT (61)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLAT_RSV2 DEBUG_PRINT_SHIFT (62)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PLAT_RSV3 DEBUG_PRINT_SHIFT (63)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define GNB_TRACE_DEFAULT\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC \</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define GNB_TRACE_REG\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORTREG_TRACE | PCIE_HOSTREG_TRACE | \</span><br><span style="color: hsl(0, 100%, 40%);">- NB_SMUREG_TRACE | GNB_TRACE_RSV1 \</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define GNB_TRACE_ALL\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- GNB_TRACE_DEFAULT | GNB_TRACE_REG \</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_TRACE_ALL\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- CPU_TRACE | CPU_TRACE_RSV1 | CPU_TRACE_RSV2 | CPU_TRACE_RSV3 | \</span><br><span style="color: hsl(0, 100%, 40%);">- CPU_TRACE_RSV4 | CPU_TRACE_RSV5 | CPU_TRACE_RSV6 | CPU_TRACE_RSV7 | \</span><br><span style="color: hsl(0, 100%, 40%);">- CPU_TRACE_RSV8 | CPU_TRACE_RSV9\</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEMORY_TRACE_ALL\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \</span><br><span style="color: hsl(0, 100%, 40%);">- MEM_UNDEF_BF | MEM_PMU | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \</span><br><span style="color: hsl(0, 100%, 40%);">- MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEMORY_TRACE_DEFAULT\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- MEM_FLOW | MEM_STATUS | MEM_PMU\</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOPO_TRACE_ALL\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- TOPO_TRACE | TOPO_TRACE_RSV1 | TOPO_TRACE_RSV2 | TOPO_TRACE_RSV3 | \</span><br><span style="color: hsl(0, 100%, 40%);">- TOPO_TRACE_RSV4 | TOPO_TRACE_RSV5 | TOPO_TRACE_RSV6 | TOPO_TRACE_RSV7 | \</span><br><span style="color: hsl(0, 100%, 40%);">- TOPO_TRACE_RSV8 | TOPO_TRACE_RSV9\</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_TRACE_ALL\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_TRACE | FCH_TRACE_RSV1 | FCH_TRACE_RSV2 | FCH_TRACE_RSV3 | \</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_TRACE_RSV4 | FCH_TRACE_RSV5 | FCH_TRACE_RSV6 | FCH_TRACE_RSV7 | \</span><br><span style="color: hsl(0, 100%, 40%);">- FCH_TRACE_RSV8 | FCH_TRACE_RSV9\</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_TRACE_ALL\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_TRACE | BVM_TRACE | IDS_TRACE_RSV2 | IDS_TRACE_RSV3\</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define OTHER_TRACE_ALL\</span><br><span style="color: hsl(0, 100%, 40%);">- (\</span><br><span style="color: hsl(0, 100%, 40%);">- MAIN_FLOW | EVENT_LOG | PERFORMANCE_ANALYSE\</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull)</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDS_DEBUG_PRINT_MASK</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEMORY_TRACE_DEFAULT | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// if no specific define INIT & EXIT will be NULL</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_HDT_CONSOLE_INIT(x)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_HDT_CONSOLE_EXIT(x)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// AGESA tracing service</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_TRACING_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef VA_ARGS_SUPPORTED</span><br><span style="color: hsl(0, 100%, 40%);">- #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__)</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #pragma warning(disable: 4127)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \</span><br><span style="color: hsl(0, 100%, 40%);">- else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \</span><br><span style="color: hsl(0, 100%, 40%);">- else if (f == TOPO_TRACE) AmdIdsDebugPrintTopology (s, __VA_ARGS__); \</span><br><span style="color: hsl(0, 100%, 40%);">- else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \</span><br><span style="color: hsl(0, 100%, 40%);">- else AmdIdsDebugPrint (f, s, __VA_ARGS__)</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE AmdIdsDebugPrint</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #define CONSOLE AmdIdsDebugPrintAll</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) Code</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsDebugPrint</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)</span><br><span style="color: hsl(0, 100%, 40%);">- #define CONSOLE CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_TIMEOUT_CTL(t)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// Macros for serial port tracing</span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef IDSOPT_SERIAL_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_SERIAL_PORT IDSOPT_SERIAL_PORT</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDS_SERIAL_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_SERIAL_PORT 0x3F8</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// Macros for redirect IO tracing</span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef IDSOPT_DEBUG_PRINT_IO_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_PRINT_IO_PORT IDSOPT_DEBUG_PRINT_IO_PORT</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IDS_DEBUG_PRINT_IO_PORT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DEBUG_PRINT_IO_PORT 0x80</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_DPRAM_BASE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_DPRAM_SIZE 0</span><br><span style="color: hsl(0, 100%, 40%);">-///Default policy, shift the old data when buffer full</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL FALSE</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_TRACING_CONSOLE_RAM == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDSOPT_DPRAM_BASE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_DPRAM_BASE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DPRAM_BASE IDSOPT_DPRAM_BASE</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #error "Debug Print Ram Base not specified, please define IDSOPT_DPRAM_BASE in optionsids.h"</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDSOPT_DPRAM_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_DPRAM_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DPRAM_SIZE IDSOPT_DPRAM_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- #else</span><br><span style="color: hsl(0, 100%, 40%);">- #error "Debug Print Ram size not specified, please define IDSOPT_DPRAM_SIZE in optionsids.h"</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Macros to add HDT OUT</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * The default minimal action is to do nothing and there is no any code to increase.</span><br><span style="color: hsl(0, 100%, 40%);">- * For debug environments, the debug information can be displayed in HDT or other</span><br><span style="color: hsl(0, 100%, 40%);">- * devices.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_HDT_CONSOLE_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_HDT_CONSOLE_EXIT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_INIT(x) AmdIdsHdtOutInit (x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_EXIT(x) AmdIdsHdtOutExit (x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_S3_EXIT(x) AmdIdsHdtOutS3Exit (x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) AmdIdsHdtOutS3ApExit (x)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) AmdIdsHdtOutBufferFlush (x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_ASSERT(x) AmdIdsDebugPrintAssert (x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_FUNCLIST_ADDR ScriptFuncList</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[]</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_S3_EXIT(x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_ASSERT(x)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_FUNCLIST_ADDR NULL</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_FUNCLIST_EXTERN()</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_TRACING_ENABLED == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_HDT_CONSOLE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE IDSOPT_CUSTOMIZE_TRACING_SERVICE</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_HDT_CONSOLE_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_INIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT (x)</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IDS_HDT_CONSOLE_EXIT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_HDT_CONSOLE_EXIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT (x)</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_PERF_ANALYSIS == TRUE</span><br><span style="color: hsl(0, 100%, 40%);">- #include "IdsPerf.h"</span><br><span style="color: hsl(0, 100%, 40%);">- #ifdef STOP_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef STOP_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #endif</span><br><span style="color: hsl(0, 100%, 40%);">- #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \</span><br><span style="color: hsl(0, 100%, 40%);">- ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \</span><br><span style="color: hsl(0, 100%, 40%);">- (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_PERF_TIMESTAMP(ID, StdHeader) IdsPerfTimestamp (STOP_CODE, ID, (StdHeader))</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_PERF_ANALYSE(StdHeader) IdsPerfAnalyseTimestamp (StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_PERF_TIMESTAMP(ID, StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_PERF_ANALYSE(StdHeader)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// Function entry for HDT script to call</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct _SCRIPT_FUNCTION {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 FuncAddr; ///< Function address in ROM</span><br><span style="color: hsl(0, 100%, 40%);">- CHAR8 FuncName[40]; ///< Function name</span><br><span style="color: hsl(0, 100%, 40%);">-} SCRIPT_FUNCTION;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// Data Structure for Mem ECC parameter override</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- IN BOOLEAN CfgEccRedirection; ///< ECC Redirection</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate</span><br><span style="color: hsl(0, 100%, 40%);">- IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood</span><br><span style="color: hsl(0, 100%, 40%);">-} ECC_OVERRIDE_STRUCT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * AGESA Test Points</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * These are the values displayed to the user to indicate progress through boot.</span><br><span style="color: hsl(0, 100%, 40%);">- * These can be used in a debug environment to stop the debugger at a specific</span><br><span style="color: hsl(0, 100%, 40%);">- * test point:</span><br><span style="color: hsl(0, 100%, 40%);">- * For SimNow!, this command</span><br><span style="color: hsl(0, 100%, 40%);">- * bi 81 w vb 49</span><br><span style="color: hsl(0, 100%, 40%);">- * will stop the debugger on one of the TracePoints (49 is the TP value in this example).</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-typedef enum {</span><br><span style="color: hsl(0, 100%, 40%);">- StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Memory test points</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemDramInit, ///< 04 .. DRAM initialization</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSPDChecking, ///< 05 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemModeChecking, ///< 06 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSpdTiming, ///< 08 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemDramMapping, ///< 09 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemPlatformSpecificConfig, ///< 0A ..</span><br><span style="color: hsl(0, 100%, 40%);">- TPProcMemPhyCompensation, ///< 0B ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemStartDcts, ///< 0C ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBeforeDramInit, ///< 0D .. (Public interface)</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemPhyFenceTraining, ///< 0E ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSynchronizeDcts, ///< 0F ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSystemMemoryMapping, ///< 10 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemMtrrConfiguration, ///< 11 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemDramTraining, ///< 12 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemWriteLevelizationTraining, ///< 14 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemReceiverEnableTraining, ///< 1A ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemReceiveDqsTraining, ///< 21 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvDqsResults, ///< 28 .. Update results</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemTransmitDqsTraining, ///< 2A ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemTxDqResults, ///< 30 .. Update results</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemMaxRdLatencyTraining, ///< 32 ..</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemEccInitialization, ///< 3C .. ECC initialization</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemLvDdr3, ///< 48 .. Before LV DDR3</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemInitMCT, ///< 49 .. Before InitMCT</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemOtherTiming, ///< 4A.. Before OtherTiming</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemMemClr, ///< 4D .. Before MemClr</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemDmi, ///< 4F .. Before DMI</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemEnd, ///< 50 .. End of memory code</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // CPU test points</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcS3Init, ///< 56 Entry point S3Init</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuProcessRegisterTables = 0X58, ///< 58 .. Register table processing</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuSetBrandID, ///< 59 .. Set brand ID</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuLoadUcode, ///< 5B .. Load microcode patch</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuCoreLeveling, ///< 5F .. Core Leveling</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuBeforeRelinquishAPsFeatureInit = 0x63, ///< 63 .. Before Relinquishing control of APs feature dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuBeforeAllocateSsdtBuffer = 0x6A, ///< 6A .. Before the P-state init code calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEntryCrat, ///< 6C .. Entry point CreateAcpiCrat</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEntryCdit, ///< 6D .. Entry point CreateAcpiCdit</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEntryScs, ///< 6E .. Entry point InitializeScsFeature</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuRunBtc, ///< 6F .. Start of Btc run</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcCpuEndBtc, ///< 70 .. End of Btc run</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Topology test points</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcTopologyEntry = 0x71, ///< 71 .. Topology Init begin</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcTopologyDone = 0x7C, ///< 7C .. Topology Init complete</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Extended memory test point</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSendMRS3, ///< 81 .. Sedding MRS3</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSendMRS1, ///< 82 .. Sending MRS1</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSendMRS0, ///< 83 .. Sending MRS0</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMem2dRdDqsTraining, ///< 86 .. Mem: 2d RdDqs Training begin</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemBefore2dTrainExtVrefChange,///< 87 .. Mem: Before optional callout to platform BIOS to change External Vref during 2d Training</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemAfter2dTrainExtVrefChange, ///< 88 .. Mem: After optional callout to platform BIOS to change External Vref during 2d Training</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemConfigureDCTForGeneral, ///< 89 .. Configure DCT For General use begin</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemProcConfigureDCTForTraining, ///< 8A .. Configure DCT For training begin</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemLvDdr4, ///< 8E .. Before LV DDR4</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Gnb Earlier init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbEarlierPcieConfigurationInit = 0x90, ///< 90 .. GNB earlier PCIE configuration init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbEarlierInterface = 0x91, ///< 91 .. GNB earlier interface</span><br><span style="color: hsl(0, 100%, 40%);">- // Gnb Early init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbEarlyInterface = 0x92, ///< 92 .. GNB early interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPcieConfigurationMap, ///< 93 .. GNB early PCIE configuration map</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPcieEarlyInterface, ///< 94 .. GNB early PCIE interface</span><br><span style="color: hsl(0, 100%, 40%);">- //Gnb post init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPciePostEarlyInterface = 0x95, ///< 95 .. GNB post early interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbGfxConfigPostInterface, ///< 96 .. GNB post GFX config interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbGfxPostInterface, ///< 97 .. GNB post GFX interface</span><br><span style="color: hsl(0, 100%, 40%);">- // Gnb post after DRAM init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPostInterface = 0x98, ///< 98 .. GNB post after DRAM interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPciePostInterface, ///< 99 .. GNB post after DRAM PCIE interface</span><br><span style="color: hsl(0, 100%, 40%);">- // Gnb Env init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbEnvInterface, ///< 9A .. GNB Env Nb interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPcieEnvInterface, ///< 9B .. GNB Env PCIE interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbGfxConfigEnvInterface, ///< 9C .. GNB Env GFX Config interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbGfxEnvInterface, ///< 9D .. GNB Env GFX interface</span><br><span style="color: hsl(0, 100%, 40%);">- // Gnb Mid init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbGfxConfigMidInterface = 0x9E, ///< 9E .. GNB Mid GFX config interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbGfxMidInterface, ///< 9F .. GNB Mid GFX interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpPcieMidInterface, ///< A0 .. GNB Mid PCIE interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbMidInterface, ///< A1 .. GNB Mid interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbSmuMidInterface, ///< A2 .. GNB Mid SMU feature</span><br><span style="color: hsl(0, 100%, 40%);">- TpPciePowerGateFeature, ///< A3 .. GNB Mid pcie power gate feature</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPcieMaxPayloadInterface, ///< A4 .. GNB Mid pcie max payload interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPcieClkPmInterface, ///< A5 .. GNB Mid pcie clk pm port interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPcieAspmInterface, ///< A6 .. GNB Mid pcie ASPM interface</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbNbIoapicInterface, ///< A7 .. GNB Mid IOAPIC interface</span><br><span style="color: hsl(0, 100%, 40%);">- // Gnb Late init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbPcieAlibFeature = 0xA8, ///< A8 .. GNB Late pcie ALIB feature</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbIommuIvrsTable, ///< A9 .. GNB Late pcie IOMMU</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbBtcRun, ///< AA .. GNB Late run BTC</span><br><span style="color: hsl(0, 100%, 40%);">- // Gnb S3 Save</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbGfxInitSview = 0xAE, ///< AD .. GNB S3SAVE GFX sview init</span><br><span style="color: hsl(0, 100%, 40%);">- TpGnbAlibDispatchFeature = 0xAE, ///< AE .. GNB ALIB dispatch feature</span><br><span style="color: hsl(0, 100%, 40%);">- EndGnbTestPoints = 0xAF, ///< AF End of TP range for GNB</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point</span><br><span style="color: hsl(0, 100%, 40%);">- EndFchTestPoints, ///< BF End of TP range for FCH</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Interface test points</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitRtbEntry, ///< CE .. Entry to AmdInitRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitRtbExit, ///< CF .. Exiting from AmdInitRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer</span><br><span style="color: hsl(0, 100%, 40%);">- TpReadyToBoot, ///< F8 .. Ready to boot event</span><br><span style="color: hsl(0, 100%, 40%);">- // PMU test points</span><br><span style="color: hsl(0, 100%, 40%);">- TpProcMemPmuFailed, ///< F9 .. Failed PMU training.</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdS3FinalRestoreEntry, ///< FA .. Entry to AmdS3FinalRestore</span><br><span style="color: hsl(0, 100%, 40%);">- TpIfAmdS3FinalRestoreExit, ///< FB .. Exiting from AmdS3FinalRestore</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- EndAgesaTps = 0xFF, ///< Last defined AGESA TP</span><br><span style="color: hsl(0, 100%, 40%);">-} AGESA_TP;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///Ids Feat description</span><br><span style="color: hsl(0, 100%, 40%);">-typedef enum {</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_DCT_ALLCKE, ///< Feat for all CKE</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_DCT_ALLCS, ///< Feat for all CS</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_HDTOUT, ///< Feat for hdt out</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_COMMON, ///< Common Feat</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT_END = 0xFF ///< End of Common feat</span><br><span style="color: hsl(0, 100%, 40%);">-} IDS_FEAT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///Ids IDT table function ID</span><br><span style="color: hsl(0, 100%, 40%);">-typedef enum {</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector</span><br><span style="color: hsl(0, 100%, 40%);">-} IDS_IDT_FUNC_ID;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef IDS_STATUS IDS_COMMON_FUNC (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT VOID *DataPtr,</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader,</span><br><span style="color: hsl(0, 100%, 40%);">- IN IDS_NV_ITEM *IdsNvPtr</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// Data Structure of IDS Feature block</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct _IDS_FAMILY_FEAT_STRUCT {</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_FEAT IdsFeat; ///< Ids Feat ID</span><br><span style="color: hsl(0, 100%, 40%);">- BOOLEAN IsBsp; ///< swith for Bsp check</span><br><span style="color: hsl(0, 100%, 40%);">- AGESA_IDS_OPTION IdsOption; ///< IDS option</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 CpuFamily; ///<</span><br><span style="color: hsl(0, 100%, 40%);">- PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function</span><br><span style="color: hsl(0, 100%, 40%);">-} IDS_FAMILY_FEAT_STRUCT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// Data Structure of IDS option</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct _IDS_OPTION_STRUCT {</span><br><span style="color: hsl(0, 100%, 40%);">- AGESA_IDS_OPTION idsoption; ///< IDS option</span><br><span style="color: hsl(0, 100%, 40%);">- PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function</span><br><span style="color: hsl(0, 100%, 40%);">-} IDS_OPTION_STRUCT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// Data Structure of IDS option table</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct _IDS_OPTION_STRUCT_TBL {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 version; ///<Version of IDS option table</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 size; ///<Size of IDS option table</span><br><span style="color: hsl(0, 100%, 40%);">- CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure</span><br><span style="color: hsl(0, 100%, 40%);">-} IDS_OPTION_STRUCT_TBL;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_NV_TO_CMOS_LEN_BYTE 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_NV_TO_CMOS_LEN_WORD 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_NV_TO_CMOS_LEN_END 0xFF</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDS_NV_TO_CMOS_ID_END 0xFFFF</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// Data struct of set/get NV to/from CMOS</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct _IDS_NV_TO_CMOS {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Length; ///< Length of NV</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 IDS_NV_ID; ///< IDS id</span><br><span style="color: hsl(0, 100%, 40%);">-} IDS_NV_TO_CMOS;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-IDS_STATUS</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsCtrlDispatcher (</span><br><span style="color: hsl(0, 100%, 40%);">- IN AGESA_IDS_OPTION IdsOption,</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT VOID *DataPtr,</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-AGESA_STATUS</span><br><span style="color: hsl(0, 100%, 40%);">-IdsOptionCallout (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINTN CallOutId,</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT VOID *DataPtr,</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsHdtOutInit (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsHdtOutExit (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsHdtOutS3Exit (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsHdtOutS3ApExit (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsDebugPrint (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT64 Flag,</span><br><span style="color: hsl(0, 100%, 40%);">- IN CONST CHAR8 *Format,</span><br><span style="color: hsl(0, 100%, 40%);">- IN ...</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsDebugPrintTopology (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CONST CHAR8 *Format,</span><br><span style="color: hsl(0, 100%, 40%);">- IN ...</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsDebugPrintCpu (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CONST CHAR8 *Format,</span><br><span style="color: hsl(0, 100%, 40%);">- IN ...</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsDebugPrintMem (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CONST CHAR8 *Format,</span><br><span style="color: hsl(0, 100%, 40%);">- IN ...</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsDebugPrintGnb (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CONST CHAR8 *Format,</span><br><span style="color: hsl(0, 100%, 40%);">- IN ...</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsDebugPrintAll (</span><br><span style="color: hsl(0, 100%, 40%);">- IN CONST CHAR8 *Format,</span><br><span style="color: hsl(0, 100%, 40%);">- IN ...</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-AmdIdsHdtOutBufferFlush (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-IdsMemTimeOut (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT VOID *DataPtr</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-IdsAgesaTestPoint (</span><br><span style="color: hsl(0, 100%, 40%);">- IN AGESA_TP TestPoint,</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * IDS Backend Function for ASSERT</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that</span><br><span style="color: hsl(0, 100%, 40%);">- * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,</span><br><span style="color: hsl(0, 100%, 40%);">- * to help distinguish the stop code from a post code loop.</span><br><span style="color: hsl(0, 100%, 40%);">- * Additional features may be available if using simulation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @retval TRUE No error</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-BOOLEAN</span><br><span style="color: hsl(0, 100%, 40%);">-IdsAssert (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 FileCode</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * The engine code for ASSERT MACRO</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that</span><br><span style="color: hsl(0, 100%, 40%);">- * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,</span><br><span style="color: hsl(0, 100%, 40%);">- * to help distinguish the stop code from a post code loop.</span><br><span style="color: hsl(0, 100%, 40%);">- * Additional features may be available if using simulation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-BOOLEAN</span><br><span style="color: hsl(0, 100%, 40%);">-IdsErrorStop (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 FileCode</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-IdsDelay (</span><br><span style="color: hsl(0, 100%, 40%);">- VOID</span><br><span style="color: hsl(0, 100%, 40%);">-);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-BOOLEAN</span><br><span style="color: hsl(0, 100%, 40%);">-AmdHeapIntactCheck (</span><br><span style="color: hsl(0, 100%, 40%);">- IN AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-IdsCarCorruptionCheck (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-IDS_STATUS</span><br><span style="color: hsl(0, 100%, 40%);">-IdsExceptionTrap (</span><br><span style="color: hsl(0, 100%, 40%);">- IN IDS_IDT_FUNC_ID IdsIdtFuncId,</span><br><span style="color: hsl(0, 100%, 40%);">- IN VOID *DataPtr,</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-AGESA_STATUS</span><br><span style="color: hsl(0, 100%, 40%);">-IdsPerfTimestamp (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 LineInFile,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 Description,</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-AGESA_STATUS</span><br><span style="color: hsl(0, 100%, 40%);">-IdsPerfAnalyseTimestamp (</span><br><span style="color: hsl(0, 100%, 40%);">- IN OUT AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- );</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IDSOPT_IDS_ENABLED == FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IEM_SKIP_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #undef IEM_INSERT_CODE</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IEM_SKIP_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IEM_SKIP_CODE(L)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef IEM_INSERT_CODE</span><br><span style="color: hsl(0, 100%, 40%);">- #define IEM_INSERT_CODE(L, Fn, Parm)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif // _IDS_H_</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h b/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h</span><br><span>deleted file mode 100644</span><br><span>index 40feef6..0000000</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Include/IdsPerf.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,148 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/* $NoKeywords:$ */</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @file</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * AMD Integrated Debug Routines for performance analysis</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Contains AMD AGESA debug macros and functions for performance analysis</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @xrefitem bom "File Content Label" "Release Content"</span><br><span style="color: hsl(0, 100%, 40%);">- * @e project: AGESA</span><br><span style="color: hsl(0, 100%, 40%);">- * @e sub-project: IDS</span><br><span style="color: hsl(0, 100%, 40%);">- * @e \$Revision$ @e \$Date$</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- /*****************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * All rights reserved.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Redistribution and use in source and binary forms, with or without</span><br><span style="color: hsl(0, 100%, 40%);">- * modification, are permitted provided that the following conditions are met:</span><br><span style="color: hsl(0, 100%, 40%);">- * * Redistributions of source code must retain the above copyright</span><br><span style="color: hsl(0, 100%, 40%);">- * notice, this list of conditions and the following disclaimer.</span><br><span style="color: hsl(0, 100%, 40%);">- * * Redistributions in binary form must reproduce the above copyright</span><br><span style="color: hsl(0, 100%, 40%);">- * notice, this list of conditions and the following disclaimer in the</span><br><span style="color: hsl(0, 100%, 40%);">- * documentation and/or other materials provided with the distribution.</span><br><span style="color: hsl(0, 100%, 40%);">- * * Neither the name of Advanced Micro Devices, Inc. nor the names of</span><br><span style="color: hsl(0, 100%, 40%);">- * its contributors may be used to endorse or promote products derived</span><br><span style="color: hsl(0, 100%, 40%);">- * from this software without specific prior written permission.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND</span><br><span style="color: hsl(0, 100%, 40%);">- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED</span><br><span style="color: hsl(0, 100%, 40%);">- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE</span><br><span style="color: hsl(0, 100%, 40%);">- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY</span><br><span style="color: hsl(0, 100%, 40%);">- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span><br><span style="color: hsl(0, 100%, 40%);">- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;</span><br><span style="color: hsl(0, 100%, 40%);">- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND</span><br><span style="color: hsl(0, 100%, 40%);">- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT</span><br><span style="color: hsl(0, 100%, 40%);">- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS</span><br><span style="color: hsl(0, 100%, 40%);">- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <check_for_wrapper.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _IDS_PERFORMANCE_DATA_POINT</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- #define _IDS_PERFORMANCE_DATA_POINT</span><br><span style="color: hsl(0, 100%, 40%);">- #define IDS_PERF_VERSION 0x00010001ul //version number 0.1.0.1</span><br><span style="color: hsl(0, 100%, 40%);">-/// Time points performance function used</span><br><span style="color: hsl(0, 100%, 40%);">-/// N O T E: NEVER change below defination, any new TP MUST be appended to the end of this enum</span><br><span style="color: hsl(0, 100%, 40%);">- typedef enum {</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGININITENV = 0x10C, ///< BeginInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDINITENV = 0x10D, ///< EndInitEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGININITMID = 0x11E, ///< BeginInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDINITMID = 0x11F, ///< EndInitMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGININITRESET = 0x12E, ///< BeginInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDINITRESET = 0x12F, ///< EndInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBINITATRTB = 0x154, ///< BeginGnbInitAtRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBINITATRTB = 0x155, ///< EndGnbInitAtRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINDISPATCHCPUFEATURESINITRTB = 0x15A, ///< BeginDispatchCpuFeaturesInitRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDDISPATCHCPUFEATURESINITRTB = 0x15B, ///< EndDispatchCpuFeaturesInitRtb</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDCPUMID = 0x15C, ///< BeginAmdCpuEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDCPUMID = 0x15D, ///< EndAmdCpuEarly</span><br><span style="color: hsl(0, 100%, 40%);">- TP_BEGINAMDGNBMIDLATE = 0x15E, ///< BeginAmdGnbMidLate</span><br><span style="color: hsl(0, 100%, 40%);">- TP_ENDAMDAMDGNBMIDLATE = 0x15F, ///< EndAmdGnbMidLate</span><br><span style="color: hsl(0, 100%, 40%);">- IDS_TP_END ///< End of IDS TP list</span><br><span style="color: hsl(0, 100%, 40%);">- } IDS_PERF_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h b/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h</span><br><span>deleted file mode 100644</span><br><span>index d53878f..0000000</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/IDS/IdsLib.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,66 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/* $NoKeywords:$ */</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @file</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * AMD IDS Routines</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Contains AMD AGESA Integrated Debug Macros</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @xrefitem bom "File Content Label" "Release Content"</span><br><span style="color: hsl(0, 100%, 40%);">- * @e project: AGESA</span><br><span style="color: hsl(0, 100%, 40%);">- * @e sub-project: IDS</span><br><span style="color: hsl(0, 100%, 40%);">- * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-/*****************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * All rights reserved.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Redistribution and use in source and binary forms, with or without</span><br><span style="color: hsl(0, 100%, 40%);">- * modification, are permitted provided that the following conditions are met:</span><br><span style="color: hsl(0, 100%, 40%);">- * * Redistributions of source code must retain the above copyright</span><br><span style="color: hsl(0, 100%, 40%);">- * notice, this list of conditions and the following disclaimer.</span><br><span style="color: hsl(0, 100%, 40%);">- * * Redistributions in binary form must reproduce the above copyright</span><br><span style="color: hsl(0, 100%, 40%);">- * notice, this list of conditions and the following disclaimer in the</span><br><span style="color: hsl(0, 100%, 40%);">- * documentation and/or other materials provided with the distribution.</span><br><span style="color: hsl(0, 100%, 40%);">- * * Neither the name of Advanced Micro Devices, Inc. nor the names of</span><br><span style="color: hsl(0, 100%, 40%);">- * its contributors may be used to endorse or promote products derived</span><br><span style="color: hsl(0, 100%, 40%);">- * from this software without specific prior written permission.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND</span><br><span style="color: hsl(0, 100%, 40%);">- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED</span><br><span style="color: hsl(0, 100%, 40%);">- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE</span><br><span style="color: hsl(0, 100%, 40%);">- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY</span><br><span style="color: hsl(0, 100%, 40%);">- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES</span><br><span style="color: hsl(0, 100%, 40%);">- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;</span><br><span style="color: hsl(0, 100%, 40%);">- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND</span><br><span style="color: hsl(0, 100%, 40%);">- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT</span><br><span style="color: hsl(0, 100%, 40%);">- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS</span><br><span style="color: hsl(0, 100%, 40%);">- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <check_for_wrapper.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _IDS_LIB_H_</span><br><span style="color: hsl(0, 100%, 40%);">-#define _IDS_LIB_H_</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/// Data Structure of Parameters for TestPoint_TSC.</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 LineInFile; ///< Line of current time counter</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 Description; ///<Description ID</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC</span><br><span style="color: hsl(0, 100%, 40%);">-} TestPoint_TSC;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RESERVED_TP_NUMER 0x20</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY + 1 + RESERVED_TP_NUMER)</span><br><span style="color: hsl(0, 100%, 40%);">-/// Data Structure of Parameters for TP_Perf_STRUCT.</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Signature; ///< "PERF"</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Version; ///< version</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Index; ///< The Index of TP_Perf_STRUCT</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 TscInMhz; ///< Tsc counter in 1 mhz</span><br><span style="color: hsl(0, 100%, 40%);">- TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT</span><br><span style="color: hsl(0, 100%, 40%);">-} TP_Perf_STRUCT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif //_IDS_LIB_H_</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/agesa_headers.h b/src/vendorcode/amd/pi/00670F00/agesa_headers.h</span><br><span>index fb17927..e03bda5 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/agesa_headers.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/agesa_headers.h</span><br><span>@@ -22,10 +22,8 @@</span><br><span> #include "AGESA.h"</span><br><span> #include "AMD.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include "Include/Ids.h"</span><br><span> #include "Include/PlatformMemoryConfiguration.h"</span><br><span> #include "Proc/Fch/FchPlatform.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "Proc/IDS/IdsLib.h"</span><br><span> #include "Proc/Psp/PspBaseLib/PspBaseLib.h"</span><br><span> #pragma pack(pop)</span><br><span> #undef AGESA_HEADERS_ARE_WRAPPED</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28298">change 28298</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28298"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If77250c9953d9eda00496e934b689290d0de1511 </div>
<div style="display:none"> Gerrit-Change-Number: 28298 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>