<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28264">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]mb/asus/p5qc: Add mainboard<br><br>SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS<br>support for ATA. It works fine in Linux afterwards<br><br>Working:<br>- SATA on southbridge port<br>- SATA on marvel IDE controller ports (only in Linux)<br>- USB<br>- COM1<br>- PS2 Keyboard<br>- DDR2 DIMMs<br>- PCIe x16 PEG port<br>- PCI port<br>- NIC (needs a driver to set macaddress)<br><br>Not working:<br>- SeaBIOS with ATA support (long timeout marvel controller so disabled)<br>- DDR2 DIMMs in only the uneven slots<br>- DDR3 fails to get initialised during JEDEC init (those are uneven slots, which<br>might be the same problem as the previous one)<br><br>Untested:<br>- PCIe x1 ports (expected to work)<br>- sound (expected to work)<br><br>TODO:<br>add documentation<br><br>Change-Id: I4a81940707566776bd048904ca1387fea741fece<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>A src/mainboard/asus/p5qc/Kconfig<br>A src/mainboard/asus/p5qc/Kconfig.name<br>A src/mainboard/asus/p5qc/Makefile.inc<br>A src/mainboard/asus/p5qc/acpi/ec.asl<br>A src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl<br>A src/mainboard/asus/p5qc/acpi/platform.asl<br>A src/mainboard/asus/p5qc/acpi/superio.asl<br>A src/mainboard/asus/p5qc/acpi_tables.c<br>A src/mainboard/asus/p5qc/board_info.txt<br>A src/mainboard/asus/p5qc/cmos.default<br>A src/mainboard/asus/p5qc/cmos.layout<br>A src/mainboard/asus/p5qc/config_seabios<br>A src/mainboard/asus/p5qc/cstates.c<br>A src/mainboard/asus/p5qc/devicetree.cb<br>A src/mainboard/asus/p5qc/dsdt.asl<br>A src/mainboard/asus/p5qc/gpio.c<br>A src/mainboard/asus/p5qc/hda_verb.c<br>A src/mainboard/asus/p5qc/romstage.c<br>M src/northbridge/intel/x4x/raminit.c<br>M src/southbridge/intel/i82801jx/i82801jx.h<br>20 files changed, 781 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28264/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..605dfd7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/Kconfig</span><br><span>@@ -0,0 +1,51 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_ASUS_P5QC</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select ARCH_X86</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_SOCKET_LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_X4X</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_I82801JX</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_WINBOND_W83667HG_A</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_1024</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "asus/p5qc"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "P5QC"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# The MARVEL IDE controller delays SeaBIOS a lot and results in an unbootable</span><br><span style="color: hsl(120, 100%, 40%);">+# bogus disk. Compiling SeaBIOS without ATA support is a workaround.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config PAYLOAD_CONFIGFILE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_ASUS_P5QC</span><br><span>diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..d764867</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_ASUS_P5QC</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "P5QC"</span><br><span>diff --git a/src/mainboard/asus/p5qc/Makefile.inc b/src/mainboard/asus/p5qc/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..630abda</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/Makefile.inc</span><br><span>@@ -0,0 +1,15 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += cstates.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/asus/p5qc/acpi/ec.asl b/src/mainboard/asus/p5qc/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..2997587</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/acpi/ec.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/* dummy */</span><br><span>diff --git a/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e8cb26e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl</span><br><span>@@ -0,0 +1,59 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* This is board specific information:</span><br><span style="color: hsl(120, 100%, 40%);">+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCI slot */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 0, 0, 0x10},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 1, 0, 0x11},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 2, 0, 0x12},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 3, 0, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, 0, 0x11},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 1, 0, 0x12},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 2, 0, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 3, 0, 0x10},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, 0, 0x12},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 1, 0, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 2, 0, 0x10},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 3, 0, 0x11},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0003ffff, 0, 0, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+} Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qc/acpi/platform.asl b/src/mainboard/asus/p5qc/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..6c92a4e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/acpi/platform.asl</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PIC, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Remember the OS' IRQ routing choice. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Arg0, PICM)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMI I/O Trap */</span><br><span style="color: hsl(120, 100%, 40%);">+Method(TRAP, 1, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Arg0, SMIF) /* SMI Function */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, TRP0) /* Generate trap */</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (SMIF) /* Return value of SMI handler */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qc/acpi/superio.asl b/src/mainboard/asus/p5qc/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..48e70a7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/acpi/superio.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/* TODO */</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d609a0e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/acpi_tables.c</span><br><span>@@ -0,0 +1,30 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/i82801jx/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ memset((void *)gnvs, 0, sizeof(*gnvs));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->pwrs = 1; /* Power state (AC = 1) */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->apic = 1; /* Enable APIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->mpen = 1; /* Enable Multi Processing */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->cmap = 0x01; /* Enable COM 1 port */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qc/board_info.txt b/src/mainboard/asus/p5qc/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..111f2e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: desktop</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://www.asus.com/Motherboards/P5QC/</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOP-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: y</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span>diff --git a/src/mainboard/asus/p5qc/cmos.default b/src/mainboard/asus/p5qc/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..ccdb7c8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/cmos.default</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Spew</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+sata_mode=AHCI</span><br><span>diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..e1d4e2b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/cmos.layout</span><br><span>@@ -0,0 +1,97 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 5 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 10 sata_mode</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+411 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: cpu</span><br><span style="color: hsl(120, 100%, 40%);">+#424 8 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+#432 554 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1024 144 r 0 recv_enable_results</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+10 0 AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+10 1 Compatible</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 983 984</span><br><span>diff --git a/src/mainboard/asus/p5qc/config_seabios b/src/mainboard/asus/p5qc/config_seabios</span><br><span>new file mode 100644</span><br><span>index 0000000..1cc1982</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/config_seabios</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# CONFIG_ATA is not set</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/mainboard/asus/p5qc/cstates.c b/src/mainboard/asus/p5qc/cstates.c</span><br><span>new file mode 100644</span><br><span>index 0000000..aa7214d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/cstates.c</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/i82801jx/i82801jx.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_cst_entries(acpi_cstate_t **entries)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..b1e9a48</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/devicetree.cb</span><br><span>@@ -0,0 +1,123 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+# (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/x4x # Northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on # APIC cluster</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_LGA775</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_1067x # CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xACAC off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on # PCI domain</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.0 on end # PEG</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 off end # Integrated graphics controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.1 off end # Integrated graphics controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.0 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.1 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.2 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 3.3 off end # ME</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 6.0 off end # PEG 2</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/i82801jx # Southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_en" = "0x40"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set AHCI mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x3f"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_clock_request" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_traffic_monitor" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable PCIe ports 0,2,3 as slots.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_slot_implemented" = "0x31"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # GBE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.1 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.2 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.7 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCIe 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCIe 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCIe 5 MARVEL IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 on end # PCIe 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # ISA bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/winbond/w83667hg-a # Super I/O</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end # FDC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 off end # LPT1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ # Global registers</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2a = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2c = 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2d = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off end # COM2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # PS/2 keyboard & mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x72 = 12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.106 off end # SPI1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.107 off end # GIPO6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.207 off end # GIPO7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.307 on # GIPO8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe4 = 0xfb</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe5 = 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.407 off end # GIPO9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # WDT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.108 off end # GPIO 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.9 off end # GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.109 on end # GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.209 on # GPIO4</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf0 = 0x7f</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xfe = 0x07</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.309 on end # GPIO5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a on # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe4 = 0x10 # 3VSBSW# enable</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xe5 = 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0xf2 = 0xfc</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HW Monitor</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x290</span><br><span style="color: hsl(120, 100%, 40%);">+ # IRQ purposefully not assigned to prevent lockups</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.c on end # PECI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.d on end # VID_BUSSEL</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.f on end # GPIO_PP_OD</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 off end # PATA/IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # SMbus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end # IDE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/asus/p5qc/dsdt.asl b/src/mainboard/asus/p5qc/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..4888b9c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/dsdt.asl</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/i82801jx/i82801jx.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02, // DSDT revision: ACPI v2.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000001 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801jx/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/x4x/acpi/x4x.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801jx/acpi/ich10.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801jx/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/asus/p5qc/gpio.c b/src/mainboard/asus/p5qc/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..fdafafc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/gpio.c</span><br><span>@@ -0,0 +1,135 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/asus/p5qc/hda_verb.c b/src/mainboard/asus/p5qc/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..22832bb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/hda_verb.c</span><br><span>@@ -0,0 +1,45 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; either version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License, or (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* coreboot specific header */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0888,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x104382fe, // Subsystem ID</span><br><span style="color: hsl(120, 100%, 40%);">+ 13, // Number of entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Widget Verb Table */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x11, 0x99430140),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x15, 0x01011012),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x16, 0x01016011),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x17, 0x01012014),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x18, 0x01a19850),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x19, 0x02a19d60),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1b, 0x02214d20),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1d, 0x4015e601),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1e, 0x01447130),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);</span><br><span>diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..eb534ca</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/asus/p5qc/romstage.c</span><br><span>@@ -0,0 +1,107 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/i82801jx/i82801jx.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/x4x/x4x.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/bist.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/winbond/w83667hg-a/w83667hg-a.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/winbond/common/winbond.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/x4x/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_DEV PCI_DEV(0, 0x1f, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early mainboard specific GPIO setup.</span><br><span style="color: hsl(120, 100%, 40%);">+ * We should use standard gpio.h eventually</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mb_gpio_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the value for GPIO base address register and enable GPIO. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_pch_gpios(&mainboard_gpio_map);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set default GPIOs on superio: TODO (here or in ramstage) */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable IOAPIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA8(0x31ff) = 0x03;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA8(0x31ff);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO? */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(RCBA_CG) = 0xbf7f001f;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(0x3430) = 0x00000002;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(0x3f00) = 0x00000038;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void ich10_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Configure serial IRQs.*/</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ | COMA_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* HW EC */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ????? */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_romstage_entry(unsigned long bist)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 boot_path = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 s3_resume;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_init(get_initial_timestamp());</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_START_ROMSTAGE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set southbridge and Super I/O GPIOs. */</span><br><span style="color: hsl(120, 100%, 40%);">+ ich10_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+ mb_gpio_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ report_bist_failure(bist);</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_smbus();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ x4x_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ s3_resume = southbridge_detect_s3_resume();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s3_resume)</span><br><span style="color: hsl(120, 100%, 40%);">+ boot_path = BOOT_PATH_RESUME;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)</span><br><span style="color: hsl(120, 100%, 40%);">+ boot_path = BOOT_PATH_WARM_RESET;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Initializing memory\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_BEFORE_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_initialize(boot_path, spd_addrmap);</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_AFTER_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+ quick_ram_check();</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Memory initialized\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ x4x_late_init(s3_resume);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "x4x late init complete\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c</span><br><span>index 9d37ada..6715f44 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit.c</span><br><span>@@ -296,6 +296,7 @@</span><br><span> min_tCLK = MAX(min_tCLK, TCK_533MHZ);</span><br><span> break;</span><br><span> case 3: /* Only on P45 */</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0:</span><br><span> min_tCLK = MAX(min_tCLK, TCK_666MHZ);</span><br><span> break;</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>index 2e2d719..3c09746 100644</span><br><span>--- a/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>+++ b/src/southbridge/intel/i82801jx/i82801jx.h</span><br><span>@@ -99,6 +99,16 @@</span><br><span> #define D31F0_PIRQH_ROUT 0x6b</span><br><span> #define D31F0_LPC_IODEC 0x80</span><br><span> #define D31F0_LPC_EN 0x82</span><br><span style="color: hsl(120, 100%, 40%);">+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */</span><br><span style="color: hsl(120, 100%, 40%);">+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */</span><br><span> #define D31F0_GEN1_DEC 0x84</span><br><span> #define D31F0_GEN2_DEC 0x88</span><br><span> #define D31F0_GEN3_DEC 0x8c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28264">change 28264</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28264"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4a81940707566776bd048904ca1387fea741fece </div>
<div style="display:none"> Gerrit-Change-Number: 28264 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>