<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28268">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl1: Extend circuit life by clock gating and power gating<br><br>The firmware of devices connected to LPC should deassert the LPC CLKRUN#<br>signal when there is no bus activity on LPC.<br><br>Necessary changes:<br><br>- Enable LPC CLKRUN#<br>- Enable LPC PCE (Power Control Enable)<br>- Enable LPC CCE (Clock Control Enable)<br>- Remove I/O decoding range on LPC for COM 3<br><br>Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c<br>M src/soc/intel/apollolake/include/soc/pcr_ids.h<br>3 files changed, 18 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28268/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c</span><br><span>index 10eb3d3..3713683 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c</span><br><span>@@ -84,7 +84,7 @@</span><br><span> PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */</span><br><span> PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */</span><br><span> PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */</span><br><span> PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */</span><br><span> </span><br><span> /* West Community */</span><br><span>@@ -402,7 +402,7 @@</span><br><span> PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */</span><br><span> PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */</span><br><span> PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */</span><br><span> PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c</span><br><span>index 540e322..739f6f4 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c</span><br><span>@@ -25,6 +25,11 @@</span><br><span> #include <baseboard/variants.h></span><br><span> #include <variant/ptn3460.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC PCR configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_LPC_PRC 0x341c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_LPC_CCE_EN 0xf</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_LPC_PCE_EN (9 < 8)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void variant_mainboard_final(void)</span><br><span> {</span><br><span> int status;</span><br><span>@@ -39,14 +44,21 @@</span><br><span> else</span><br><span> printk(BIOS_INFO, "LCD: Set up PTN was successful.\n");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable additional I/O decoding range on LPC for COM 3 */</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_open_pmio_window(0x3e8, 8);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * PIR6 register mapping for PCIe root ports</span><br><span> * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#</span><br><span> */</span><br><span> pcr_write16(PID_ITSS, 0x314c, 0x0321);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable CLKRUN_EN for power gating LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc_enable_pci_clk_cntl();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2</span><br><span style="color: hsl(120, 100%, 40%);">+ * offset 0x341D bit3 and bit0.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2</span><br><span style="color: hsl(120, 100%, 40%);">+ * offset 0x341C bit [3:0].</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));</span><br><span> }</span><br><span> </span><br><span> static void wait_for_legacy_dev(void *unused)</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h</span><br><span>index f816693..878c45b 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/pcr_ids.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h</span><br><span>@@ -31,6 +31,7 @@</span><br><span> #define PID_GPIO_N 0xC5</span><br><span> #define PID_ITSS 0xD0</span><br><span> #define PID_RTC 0xD1</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_LPC 0xD2</span><br><span> </span><br><span> #define PID_AUNIT 0x4d</span><br><span> #define PID_BUNIT 0x4c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28268">change 28268</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 </div>
<div style="display:none"> Gerrit-Change-Number: 28268 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>