<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28270">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard<br><br>For the 1st redesign of mc_apl1 mainboard some adjustments are<br>necessary:<br><br>- The FPGA is now connected directly via a PCIe Root Port<br>- Internal Apollo Lake UARTs are now used<br>- Adjusting GPIO settings<br><br>Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb<br>2 files changed, 84 insertions(+), 84 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28270/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c</span><br><span>index 10eb3d3..02d0601 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c</span><br><span>@@ -28,70 +28,70 @@</span><br><span> /* Southwest Community */</span><br><span> </span><br><span> /* PCIE_WAKE[0:3]_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1), /* PCIE_WAKE0_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_206, UP_20K, DEEP, NF1), /* PCIE_WAKE1_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_207, UP_20K, DEEP, NF1), /* PCIE_WAKE2_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1), /* PCIE_WAKE3_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1), /* PCIE_WAKE0_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1), /* PCIE_WAKE1_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1), /* PCIE_WAKE2_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1), /* PCIE_WAKE3_N */</span><br><span> </span><br><span> /* EMMC interface. */</span><br><span> PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_157, NONE, DEEP, NF1), /* EMMC_D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_158, NONE, DEEP, NF1), /* EMMC_D1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_159, NONE, DEEP, NF1), /* EMMC_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_160, NONE, DEEP, NF1), /* EMMC_D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_161, NONE, DEEP, NF1), /* EMMC_D4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_162, NONE, DEEP, NF1), /* EMMC_D5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_163, NONE, DEEP, NF1), /* EMMC_D6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_164, NONE, DEEP, NF1), /* EMMC_D7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_165, NONE, DEEP, NF1), /* EMMC_CMD */</span><br><span> PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */</span><br><span> </span><br><span> /* SDIO -- unused */</span><br><span> PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), /* SDIO_D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */</span><br><span> /* Configure SDIO to enable power gating. */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_168, DN_20K, DEEP), /* SDIO_D1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), /* SDIO_D2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), /* SDIO_D3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), /* SDIO_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */</span><br><span> </span><br><span> /* SDCARD */</span><br><span> /* Pull down clock by 20K. */</span><br><span> PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_173, NONE, DEEP, NF1), /* SDCARD_D0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_174, NONE, DEEP, NF1), /* SDCARD_D1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_175, NONE, DEEP, NF1), /* SDCARD_D2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_176, NONE, DEEP, NF1), /* SDCARD_D3 */</span><br><span> /* Card detect is active LOW with external pull up. */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_178, NONE, DEEP, NF1), /* SDCARD_CMD */</span><br><span> /* CLK feedback, internal signal, needs 20K pull down. */</span><br><span> PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_186, UP_20K, DEEP), /* SDCARD_LVL_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_186, NONE, DEEP), /* SDCARD_LVL_WP */</span><br><span> /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */</span><br><span> PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDIO_PWR_DOWN_N */</span><br><span> </span><br><span> /* SMBus */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1), /* SMB_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1), /* SMB_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(SMB_ALERTB, NONE, DEEP), /* SMB_ALERT _N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */</span><br><span> </span><br><span> /* LPC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */</span><br><span> PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */</span><br><span> PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(LPC_CLKRUNB, NONE, DEEP), /* LPC_CLKRUN_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */</span><br><span> </span><br><span> /* West Community */</span><br><span> </span><br><span> /* I2C0 - I2C Level Shifter */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1), /* LPSS_I2C0_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1), /* LPSS_I2C0_SCL */</span><br><span> </span><br><span> /* I2C[1:7] -- unused */</span><br><span> PAD_CFG_GPI(GPIO_126, UP_20K, DEEP), /* LPSS_I2C1_SDA */</span><br><span>@@ -122,10 +122,10 @@</span><br><span> PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */</span><br><span> </span><br><span> /* PCIE_CLKREQ[0:3]_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_210, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_211, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_212, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1),</span><br><span> </span><br><span> /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */</span><br><span> PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1),</span><br><span>@@ -136,10 +136,10 @@</span><br><span> PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),</span><br><span> </span><br><span> /* PMU Signals */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP), /* PMU_AC_PRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */</span><br><span> PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */</span><br><span> PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */</span><br><span> PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */</span><br><span> /* PMU_SLP_S0_N */</span><br><span> PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE),</span><br><span>@@ -156,25 +156,25 @@</span><br><span> PAD_CFG_GPI(GPIO_187, DN_20K, DEEP), /* HV_DDI0_DDC_SDA */</span><br><span> PAD_CFG_GPI(GPIO_188, DN_20K, DEEP), /* HV_DDI0_DDC_SCL */</span><br><span> /* DDI1 SDA and SCL - Display-Port */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_189, UP_20K, DEEP, NF1), /* HV_DDI1_DDC_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_190, UP_20K, DEEP, NF1), /* HV_DDI1_DDC_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1), /* HV_DDI1_DDC_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1), /* HV_DDI1_DDC_SCL */</span><br><span> </span><br><span> /* MIPI I2C -- unused */</span><br><span> PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), /* MIPI_I2C_SDA */</span><br><span> PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), /* MIPI_I2C_SCL */</span><br><span> </span><br><span> /* Panel 0 control -- unused */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_193, DN_20K, DEEP), /* PNL0_VDDEN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_194, DN_20K, DEEP), /* PNL0_BKLTEN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_195, DN_20K, DEEP), /* PNL0_BKLTCTL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP), /* PNL0_VDDEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP), /* PNL0_BKLTEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP), /* PNL0_BKLTCTL */</span><br><span> </span><br><span> /* Panel 1 control -- unused */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_196, DN_20K, DEEP, NF1), /* PNL1_VDDEN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1), /* PNL1_BKLTEN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_198, DN_20K, DEEP, NF1), /* PNL1_BKLTCTL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */</span><br><span> </span><br><span> /* DDI[0:1]_HPD -- unused */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_199, UP_20K, DEEP), /* XHPD_DP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */</span><br><span> PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */</span><br><span> </span><br><span> /* MDSI signals -- unused */</span><br><span>@@ -182,12 +182,12 @@</span><br><span> PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */</span><br><span> </span><br><span> /* USB overcurrent pins. */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1), /* USB_OC0_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1), /* USB_OC1_N */</span><br><span> </span><br><span> /* PMC SPI -- almost entirely unused. */</span><br><span> PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* XHPD_EDP_APL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMC_SPI_FS1, NONE, DEEP, NF2), /* XHPD_EDP_APL */</span><br><span> PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP),</span><br><span> PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP),</span><br><span> PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP),</span><br><span>@@ -195,16 +195,16 @@</span><br><span> </span><br><span> /* PMIC Signals unused signals related to an old PMIC interface. */</span><br><span> PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(PMIC_RESET_B, NONE, DEEP), /* PMIC_RESET_B */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_213, DN_20K, DEEP), /* NFC_OUT_RESERVE */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* NFC_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */</span><br><span> PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* NFC_IN_RESERVE */</span><br><span> /* THERMTRIP_N */</span><br><span> PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(PMIC_STDBY, 1, DEEP), /* unused */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(PMIC_STDBY, 0, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1), /* PROCHOT_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1), /* PMIC_I2C_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1), /* PMIC_I2C_SDA */</span><br><span> </span><br><span> /* I2S1 -- unused */</span><br><span> PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */</span><br><span>@@ -271,7 +271,7 @@</span><br><span> PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */</span><br><span> PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */</span><br><span> PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* GP_SSP_2_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_123, NONE, DEEP), /* GP_SSP_2_TXD */</span><br><span> </span><br><span> /* North Community */</span><br><span> </span><br><span>@@ -296,8 +296,8 @@</span><br><span> PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), /* TRACE_1_DATA6_VNN */</span><br><span> PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), /* TRACE_1_DATA7_VNN */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_18, UP_20K, DEEP), /* TRACE_2_CLK_VNN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* TRACE_2_DATA0_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), /* TRACE_2_CLK_VNN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), /* TRACE_2_DATA0_VNN */</span><br><span> PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), /* TRACE_2_DATA1_VNN */</span><br><span> PAD_CFG_GPI(GPIO_21, DN_20K, DEEP), /* TRACE_2_DATA2_VNN */</span><br><span> PAD_CFG_GPI(GPIO_22, DN_20K, DEEP), /* TRACE_2_DATA3_VNN */</span><br><span>@@ -311,8 +311,8 @@</span><br><span> PAD_CFG_GPI(GPIO_29, DN_20K, DEEP), /* TRIGIN_0 */</span><br><span> </span><br><span> PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* ISH_GPIO_12 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_31, DN_20K, DEEP), /* ISH_GPIO_13 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_32, DN_20K, DEEP), /* ISH_GPIO_14 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_31, 1, DEEP), /* ISH_GPIO_13 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_32, NONE, DEEP), /* ISH_GPIO_14 */</span><br><span> PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* ISH_GPIO_15 */</span><br><span> </span><br><span> /* PWM[0:3] -- unused */</span><br><span>@@ -326,7 +326,7 @@</span><br><span> PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */</span><br><span> PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */</span><br><span> PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPIO_42, UP_20K, DEEP), /* LPSS_UART1_RXD - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_42, NONE, DEEP), /* LPSS_UART1_RXD - unused */</span><br><span> PAD_CFG_GPI(GPIO_43, DN_20K, DEEP), /* LPSS_UART1_TXD - unused */</span><br><span> PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */</span><br><span> PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */</span><br><span>@@ -390,20 +390,20 @@</span><br><span> PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */</span><br><span> </span><br><span> /* SMBus */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1), /* SMB_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1), /* SMB_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */</span><br><span> </span><br><span> /* LPC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), /* LPC_CLKOUT0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */</span><br><span> /* LPC_CLKOUT1 - unused */</span><br><span> PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(LPC_CLKRUNB, NONE, DEEP), /* LPC_CLKRUN_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */</span><br><span> };</span><br><span> </span><br><span> const struct pad_config *__weak</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb</span><br><span>index 4d9c655..a273a59 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb</span><br><span>@@ -8,7 +8,7 @@</span><br><span> </span><br><span> # Disable unused clkreq of PCIe root ports</span><br><span> register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp_clkreq_pin[1]" = "2" # FPGA</span><br><span> register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY</span><br><span> register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY</span><br><span> register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span>@@ -73,7 +73,7 @@</span><br><span> device pci 13.2 off end # - RP 4 - PCIe-A 2</span><br><span> device pci 13.3 off end # - RP 5 - PCIe-A 3</span><br><span> device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.1 off end # - RP 1 - PCIe-B 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA</span><br><span> device pci 15.0 on end # - XHCI</span><br><span> device pci 15.1 off end # - XDCI</span><br><span> device pci 16.0 on # - I2C 0</span><br><span>@@ -98,10 +98,10 @@</span><br><span> device pci 17.1 off end # - I2C 5</span><br><span> device pci 17.2 off end # - I2C 6</span><br><span> device pci 17.3 on end # - I2C 7</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.0 off end # - UART 0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.1 off end # - UART 1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.2 off end # - UART 2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 18.3 off end # - UART 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end # - UART 0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 on end # - UART 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end # - UART 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 on end # - UART 3</span><br><span> device pci 19.0 off end # - SPI 0</span><br><span> device pci 19.1 off end # - SPI 1</span><br><span> device pci 19.2 off end # - SPI 2</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28270">change 28270</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28270"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57 </div>
<div style="display:none"> Gerrit-Change-Number: 28270 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>