<p>Angel Pons has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28231">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Documentation/northbridge/intel/sandybridge/*: fix typos<br><br>Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in<br>text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy<br>Bridge".<br><br>Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a<br>Signed-off-by: Angel Pons <th3fanbus@gmail.com><br>---<br>M Documentation/northbridge/intel/sandybridge/nri.md<br>M Documentation/northbridge/intel/sandybridge/nri_freq.md<br>M Documentation/northbridge/intel/sandybridge/nri_read.md<br>M Documentation/northbridge/intel/sandybridge/nri_registers.md<br>4 files changed, 15 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28231/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md</span><br><span>index 1b07ba4..812cd23 100644</span><br><span>--- a/Documentation/northbridge/intel/sandybridge/nri.md</span><br><span>+++ b/Documentation/northbridge/intel/sandybridge/nri.md</span><br><span>@@ -3,7 +3,7 @@</span><br><span> ## Introduction</span><br><span> </span><br><span> This documentation is intended to document the closed source memory controller</span><br><span style="color: hsl(0, 100%, 40%);">-hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs.</span><br><span style="color: hsl(120, 100%, 40%);">+hardware for Intel 2nd Gen (Sandy Bridge) and 3rd Gen (Ivy Bridge) core-i CPUs.</span><br><span> </span><br><span> The memory initialization code has to take care of lots of duties:</span><br><span> 1. Selection of operating frequency</span><br><span>@@ -41,13 +41,13 @@</span><br><span> ```</span><br><span> </span><br><span> ## (Inoffical) register documentation</span><br><span style="color: hsl(0, 100%, 40%);">-- [Sandy Bride - Register documentation](nri_registers.md)</span><br><span style="color: hsl(120, 100%, 40%);">+- [Sandy Bridge - Register documentation](nri_registers.md)</span><br><span> </span><br><span> ## Frequency selection</span><br><span style="color: hsl(0, 100%, 40%);">-- [Sandy Bride - Frequency selection](nri_freq.md)</span><br><span style="color: hsl(120, 100%, 40%);">+- [Sandy Bridge - Frequency selection](nri_freq.md)</span><br><span> </span><br><span> ## Read training</span><br><span style="color: hsl(0, 100%, 40%);">-- [Sandy Bride - Read training](nri_read.md)</span><br><span style="color: hsl(120, 100%, 40%);">+- [Sandy Bridge - Read training](nri_read.md)</span><br><span> </span><br><span> ### SMBIOS type 17</span><br><span> The SMBIOS specification allows to report the memory configuration in use.</span><br><span>@@ -113,7 +113,7 @@</span><br><span> > **Note:** This feature is available since coreboot 4.5</span><br><span> </span><br><span> Try to swap memory modules and or try to use a different vendor. If nothing</span><br><span style="color: hsl(0, 100%, 40%);">-helps you could have a look at capter [Debuggin] or report a ticket</span><br><span style="color: hsl(120, 100%, 40%);">+helps you could have a look at chapter [Debugging] or report a ticket</span><br><span> at [ticket.coreboot.org]. Please provide a full RAM init log,</span><br><span> that has been captured using EHCI debug.</span><br><span> </span><br><span>diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md</span><br><span>index d8b73b3..208c1cb 100644</span><br><span>--- a/Documentation/northbridge/intel/sandybridge/nri_freq.md</span><br><span>+++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md</span><br><span>@@ -1,7 +1,8 @@</span><br><span> # Frequency selection</span><br><span> </span><br><span> ## Introduction</span><br><span style="color: hsl(0, 100%, 40%);">-This chapter explains the frequency selection done on Sandybride and Ivybridge.</span><br><span style="color: hsl(120, 100%, 40%);">+This chapter explains the frequency selection done on Sandy Bridge and Ivy</span><br><span style="color: hsl(120, 100%, 40%);">+Bridge memory initialization.</span><br><span> </span><br><span> ## Definitions</span><br><span> ```eval_rst</span><br><span>@@ -58,7 +59,7 @@</span><br><span> </span><br><span> > **Note:** Ignoring the fuses might cause system instability !</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being</span><br><span style="color: hsl(120, 100%, 40%);">+On Sandy Bridge *CAPID0_A* is being read, and on Ivy Bridge *CAPID0_B* is being</span><br><span> read. coreboot reads those registers and honors the limit in case the Kconfig</span><br><span> option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.</span><br><span> Power users that want to let their RAM run at DRAM's "stock" frequency need to</span><br><span>@@ -84,7 +85,7 @@</span><br><span> By using this register it's possible to force a minimum operating frequency.</span><br><span> </span><br><span> ## Reference clock</span><br><span style="color: hsl(0, 100%, 40%);">-While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also</span><br><span style="color: hsl(120, 100%, 40%);">+While Sandy Bridge supports 133 MHz reference clock (REFCK), Ivy Bridge also</span><br><span> supports 100 MHz reference clock. The reference clock is multiplied by the DRAM</span><br><span> multiplier to select the DRAM frequency (SCK) by the following formula:</span><br><span> </span><br><span>@@ -92,7 +93,7 @@</span><br><span> </span><br><span> > **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-## Sandy Bride's supported frequencies</span><br><span style="color: hsl(120, 100%, 40%);">+## Sandy Bridge's supported frequencies</span><br><span> ```eval_rst</span><br><span> +------------+-----------+------------------+-------------------------+---------------+</span><br><span> | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |</span><br><span>@@ -111,7 +112,7 @@</span><br><span> +------------+-----------+------------------+-------------------------+---------------+</span><br><span> ```</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-## Ivybridge's supported frequencies</span><br><span style="color: hsl(120, 100%, 40%);">+## Ivy Bridge's supported frequencies</span><br><span> ```eval_rst</span><br><span> +------------+-----------+------------------+-------------------------+---------------+</span><br><span> | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment |</span><br><span>@@ -144,7 +145,7 @@</span><br><span> > '1: since coreboot 4.6</span><br><span> </span><br><span> ## Multiplier selection</span><br><span style="color: hsl(0, 100%, 40%);">-coreboot select the maximum frequency to operate at by the following formula:</span><br><span style="color: hsl(120, 100%, 40%);">+coreboot selects the maximum frequency to operate at by the following formula:</span><br><span> ```</span><br><span> if devicetree's max_mem_clock_mhz > 0:</span><br><span> freq_max := max_mem_clock_mhz</span><br><span>diff --git a/Documentation/northbridge/intel/sandybridge/nri_read.md b/Documentation/northbridge/intel/sandybridge/nri_read.md</span><br><span>index 0496657..f5c79ac 100644</span><br><span>--- a/Documentation/northbridge/intel/sandybridge/nri_read.md</span><br><span>+++ b/Documentation/northbridge/intel/sandybridge/nri_read.md</span><br><span>@@ -2,7 +2,7 @@</span><br><span> </span><br><span> ## Introduction</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-This chapter explains the read training sequence done on Sandy Bride and</span><br><span style="color: hsl(120, 100%, 40%);">+This chapter explains the read training sequence done on Sandy Bridge and</span><br><span> Ivy Bridge memory initialization.</span><br><span> </span><br><span> Read training is done to compensate the skew between DQS and SCK and to find</span><br><span>diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md</span><br><span>index 601157c..6249560 100644</span><br><span>--- a/Documentation/northbridge/intel/sandybridge/nri_registers.md</span><br><span>+++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md</span><br><span>@@ -1556,7 +1556,7 @@</span><br><span> </span><br><span> *Width:* 16 Bit</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-*Desc:* OTHP Workaround (SandyBridge only) Register, Channel 0</span><br><span style="color: hsl(120, 100%, 40%);">+*Desc:* OTHP Workaround (Sandy Bridge only) Register, Channel 0</span><br><span> </span><br><span> ```eval_rst</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span>@@ -2138,7 +2138,7 @@</span><br><span> | 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 8 | - 1: 100Mhz reference clock |</span><br><span style="color: hsl(0, 100%, 40%);">-| | - 0: 133Mhz reference clock (IvyBridge only) |</span><br><span style="color: hsl(120, 100%, 40%);">+| | - 0: 133Mhz reference clock (Ivy Bridge only) |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span> | 31 | PLL busy |</span><br><span> +-----------+------------------------------------------------------------------+</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28231">change 28231</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a </div>
<div style="display:none"> Gerrit-Change-Number: 28231 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> </div>