<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28227">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/foxconn/d41s: Add mainboard<br><br>This supports the Foxconn d41s, d42s, d51s, d52s.<br><br>The following is tested (SeaBIOS 1.12 + Linux 4.9) and works:<br>- COM1<br>- S3 resume (with SeaBIOS needs sercon disabled)<br>- Native graphic init on VGA output<br>- SATA<br>- USB<br><br>The base for this mainboard port was the Intel D510MO port.<br><br>Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>A src/mainboard/foxconn/d41s/Kconfig<br>A src/mainboard/foxconn/d41s/Kconfig.name<br>A src/mainboard/foxconn/d41s/Makefile.inc<br>A src/mainboard/foxconn/d41s/acpi/ec.asl<br>A src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl<br>A src/mainboard/foxconn/d41s/acpi/platform.asl<br>A src/mainboard/foxconn/d41s/acpi/superio.asl<br>A src/mainboard/foxconn/d41s/acpi_tables.c<br>A src/mainboard/foxconn/d41s/board_info.txt<br>A src/mainboard/foxconn/d41s/cmos.default<br>A src/mainboard/foxconn/d41s/cmos.layout<br>A src/mainboard/foxconn/d41s/cstates.c<br>A src/mainboard/foxconn/d41s/data.vbt<br>A src/mainboard/foxconn/d41s/devicetree.cb<br>A src/mainboard/foxconn/d41s/dsdt.asl<br>A src/mainboard/foxconn/d41s/gpio.c<br>A src/mainboard/foxconn/d41s/hda_verb.c<br>A src/mainboard/foxconn/d41s/mainboard.c<br>A src/mainboard/foxconn/d41s/romstage.c<br>19 files changed, 807 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/28227/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..56ab34f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/Kconfig</span><br><span>@@ -0,0 +1,46 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_FOXCONN_D41S</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_SOCKET_FCBGA559</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_PINEVIEW</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_I82801GX</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_ITE_IT8721F</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_1024</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_INT15</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_CK505</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_GMA_HAVE_VBT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default foxconn/d41s</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "D41S"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_FOXCONN_D41S</span><br><span>diff --git a/src/mainboard/foxconn/d41s/Kconfig.name b/src/mainboard/foxconn/d41s/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..9462f94</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_FOXCONN_D41S</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "D41S, D42S, D51S, D52S"</span><br><span>diff --git a/src/mainboard/foxconn/d41s/Makefile.inc b/src/mainboard/foxconn/d41s/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..f3d7e76</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/Makefile.inc</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += cstates.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/foxconn/d41s/acpi/ec.asl b/src/mainboard/foxconn/d41s/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..31eb392</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/acpi/ec.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/* Dummy file - No license required. */</span><br><span>diff --git a/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl b/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..23c39ef</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/acpi/ich7_pci_irqs.asl</span><br><span>@@ -0,0 +1,36 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* This is board specific information:</span><br><span style="color: hsl(120, 100%, 40%);">+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If (PICM) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 0, 0, 0x15},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 1, 0, 0x16},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 2, 0, 0x17},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 3, 0, 0x14},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, 0, 0x13},</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+} Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/foxconn/d41s/acpi/platform.asl b/src/mainboard/foxconn/d41s/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..6c92a4e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/acpi/platform.asl</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PIC, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Remember the OS' IRQ routing choice. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Arg0, PICM)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMI I/O Trap */</span><br><span style="color: hsl(120, 100%, 40%);">+Method(TRAP, 1, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Arg0, SMIF) /* SMI Function */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, TRP0) /* Generate trap */</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (SMIF) /* Return value of SMI handler */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/foxconn/d41s/acpi/superio.asl b/src/mainboard/foxconn/d41s/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..241a40c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/acpi/superio.asl</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 secunet Security Networks AG</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Samuel Holland <samuel@sholland.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef SUPERIO_DEV</span><br><span style="color: hsl(120, 100%, 40%);">+#undef SUPERIO_PNP_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+#undef IT8721F_SHOW_SP1</span><br><span style="color: hsl(120, 100%, 40%);">+#undef IT8721F_SHOW_SP2</span><br><span style="color: hsl(120, 100%, 40%);">+#undef IT8721F_SHOW_EC</span><br><span style="color: hsl(120, 100%, 40%);">+#undef IT8721F_SHOW_KBCK</span><br><span style="color: hsl(120, 100%, 40%);">+#undef IT8721F_SHOW_KBCM</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV SIO0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_PNP_BASE 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define IT8721F_SHOW_SP1</span><br><span style="color: hsl(120, 100%, 40%);">+#define IT8721F_SHOW_EC</span><br><span style="color: hsl(120, 100%, 40%);">+#define IT8721F_SHOW_KBCK</span><br><span style="color: hsl(120, 100%, 40%);">+#define IT8721F_SHOW_KBCM</span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/it8721f/acpi/superio.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/foxconn/d41s/acpi_tables.c b/src/mainboard/foxconn/d41s/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..92688bf</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/acpi_tables.c</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/i82801gx/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/foxconn/d41s/board_info.txt b/src/mainboard/foxconn/d41s/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..7b9a700</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/board_info.txt</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: desktop</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000481</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: DIP-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: y</span><br><span>diff --git a/src/mainboard/foxconn/d41s/cmos.default b/src/mainboard/foxconn/d41s/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..41098be</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/cmos.default</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Debug</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+gfx_uma_size=8M</span><br><span>diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..9b9a084</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/cmos.layout</span><br><span>@@ -0,0 +1,90 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 2 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#400 8 r 0 reserved for century byte</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: bootloader</span><br><span style="color: hsl(120, 100%, 40%);">+416 512 s 0 boot_devices</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: cpu</span><br><span style="color: hsl(120, 100%, 40%);">+944 1 e 2 hyper_threading</span><br><span style="color: hsl(120, 100%, 40%);">+#945 7 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+952 3 e 11 gfx_uma_size</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+11 0 8M</span><br><span style="color: hsl(120, 100%, 40%);">+11 1 16M</span><br><span style="color: hsl(120, 100%, 40%);">+11 2 32M</span><br><span style="color: hsl(120, 100%, 40%);">+11 3 48M</span><br><span style="color: hsl(120, 100%, 40%);">+11 4 64M</span><br><span style="color: hsl(120, 100%, 40%);">+11 5 128M</span><br><span style="color: hsl(120, 100%, 40%);">+11 6 256M</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 983 984</span><br><span>diff --git a/src/mainboard/foxconn/d41s/cstates.c b/src/mainboard/foxconn/d41s/cstates.c</span><br><span>new file mode 100644</span><br><span>index 0000000..b7eb6df</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/cstates.c</span><br><span>@@ -0,0 +1,22 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/x86/include/arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int get_cst_entries(acpi_cstate_t **entries)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/foxconn/d41s/data.vbt b/src/mainboard/foxconn/d41s/data.vbt</span><br><span>new file mode 100644</span><br><span>index 0000000..5570737</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/data.vbt</span><br><span>Binary files differ</span><br><span>diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..616ed2b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/devicetree.cb</span><br><span>@@ -0,0 +1,99 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+# (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/pineview # Northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.use_spread_spectrum_clock" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "use_crt" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "use_lvds" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on # APIC cluster</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_FCBGA559 # CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end # APIC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on # PCI domain</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1.0 off end # PEG</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.0 on end # Integrated graphics controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 2.1 off end # Integrated graphics controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/i82801gx # Southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ahci" = "0x1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ports_implemented" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_en" = "0x441"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # PCIe 2 (NIC)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCIe 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCIe 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.7 on end # USB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # ISA bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/ite/it8721f # Super I/O</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end # Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 off end # COM2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 off end # PP</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.4 on # EC</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0xa10</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0xa00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # PS/2 keyboard / mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 1 # PS/2 keyboard interrupt</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 on # PS/2 mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 12</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off end # GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a off end # CIR</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on # SMbus</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/ck505</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mask" = "{ 0x00, 0x80, 0xff, 0xff,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xff }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "regs" = "{ 0x00, 0x80, 0xfe, 0xff,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xfc }"</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 69 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/foxconn/d41s/dsdt.asl b/src/mainboard/foxconn/d41s/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..621b87d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/dsdt.asl</span><br><span>@@ -0,0 +1,41 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02, // DSDT revision: ACPI v2.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20090419 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/speedstep/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/pineview/acpi/pineview.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801gx/acpi/ich7.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/foxconn/d41s/gpio.c b/src/mainboard/foxconn/d41s/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e88e4db</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/gpio.c</span><br><span>@@ -0,0 +1,163 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio58 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio63 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/foxconn/d41s/hda_verb.c b/src/mainboard/foxconn/d41s/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..dbe383e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/hda_verb.c</span><br><span>@@ -0,0 +1,39 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* coreboot specific header */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0662,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x105b0d55, // Subsystem ID</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000000a, // Number of entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pin Widget Verb Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x14, 0x01014c10),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x18, 0x01a19c30),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c31),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1a, 0x0181343f),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1e, 0x99430120),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/foxconn/d41s/mainboard.c b/src/mainboard/foxconn/d41s/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d2751bc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/mainboard.c</span><br><span>@@ -0,0 +1,30 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ops.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/int15.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c996c5f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/foxconn/d41s/romstage.c</span><br><span>@@ -0,0 +1,146 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/i82801gx/i82801gx.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/pineview/raminit.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/pineview/pineview.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/bist.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/common/ite.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/ite/it8721f/it8721f.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/stages.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early mainboard specific GPIO setup */</span><br><span style="color: hsl(120, 100%, 40%);">+static void mb_gpio_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Southbridge GPIOs. */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = PCI_DEV(0x0, 0x1f, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the value for GPIO base address register and enable GPIO. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, GPIO_CNTL, 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_pch_gpios(&mainboard_gpio_map);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void nm10_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable Serial IRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Decode range */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN</span><br><span style="color: hsl(120, 100%, 40%);">+ | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Environment Controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set up virtual channel 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(0x0014) = 0x80000001;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(0x001c) = 0x03128010;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable IOAPIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA8(OIC) = 0x03;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD | FD_ACAUD</span><br><span style="color: hsl(120, 100%, 40%);">+ | FD_PATA;</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(FD) |= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_romstage_entry(unsigned long bist)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };</span><br><span style="color: hsl(120, 100%, 40%);">+ int cbmem_was_initted;</span><br><span style="color: hsl(120, 100%, 40%);">+ int s3resume = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ int boot_path;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_init(get_initial_timestamp());</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_START_ROMSTAGE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bist == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_lapic();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable watchdog timer */</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(GCS) = RCBA32(GCS) | 0x20;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set southbridge and Super I/O GPIOs. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mb_gpio_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nm10_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ report_bist_failure(bist);</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_smbus();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pineview_early_initialization();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x30);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ s3resume = southbridge_detect_s3_resume();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s3resume) {</span><br><span style="color: hsl(120, 100%, 40%);">+ boot_path = BOOT_PATH_RESUME;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */</span><br><span style="color: hsl(120, 100%, 40%);">+ boot_path = BOOT_PATH_RESET;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ boot_path = BOOT_PATH_NORMAL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Initializing memory\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_BEFORE_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_initialize(boot_path, spd_addrmap);</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_AFTER_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Memory initialized\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x31);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ quick_ram_check();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rcba_config();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cbmem_was_initted = !cbmem_recovery(s3resume);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!cbmem_was_initted && s3resume) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Failed S3 resume, reset to come up cleanly */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x6, 0xcf9);</span><br><span style="color: hsl(120, 100%, 40%);">+ halt();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ romstage_handoff_init(s3resume);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28227">change 28227</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28227"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072 </div>
<div style="display:none"> Gerrit-Change-Number: 28227 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>