<p>Kane Chen <strong>uploaded patch set #2</strong> to this change.</p><p><a href="https://review.coreboot.org/28074">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Disable usb2 phy power gating.<br><br>Currently, we found the usb2 phy registers value are restored to soc<br>default after xhci PS3, PS0 are executed.<br>This will cause some usb 2.0 devices not detected after xhci resumes<br>from D3.<br><br>Before root cause, this patch temporarily disables the usb2 phy power<br>gating in xhci PS0 PS3 so that usb2phy registers won't be restored to<br>soc default.<br><br>BUG=b:110175562<br>TEST=check usb2 phy registers are not restore to soc default.<br><br>Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d<br>Signed-off-by: Kane Chen <kane.chen@intel.com><br>---<br>M src/soc/intel/skylake/acpi/xhci.asl<br>1 file changed, 0 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28074/2</pre><p>To view, visit <a href="https://review.coreboot.org/28074">change 28074</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28074"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d </div>
<div style="display:none"> Gerrit-Change-Number: 28074 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Kane Chen <kane.chen@intel.com> </div>