<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28082">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/amd/pi/00670F00: Remove functions that use LibAmdPciRMW()<br><br>The functions that use LibAmdPciRMW() are not used by coreboot and can be<br>safely removed in preparation to remove LibAmdPciRMW() itself. The<br>functions to be removed are:<br><br>From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c:<br>ProgramPciByteTable().<br><br>From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c: RwXhciIndReg(),<br>RwXhci0IndReg() and RwXhci1IndReg().<br><br>From vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c: RwPci().<br><br>BUG=b:112541697<br>TEST=Build grunt and gardenia<br><br>Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c<br>4 files changed, 0 insertions(+), 133 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28082/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h</span><br><span>index 3f4bccf..aa11396 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h</span><br><span>@@ -55,8 +55,6 @@</span><br><span> VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);</span><br><span> VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span> VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span> VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);</span><br><span> VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl);</span><br><span> VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);</span><br><span>@@ -346,9 +344,6 @@</span><br><span> VOID BackUpCG2 (OUT VOID);</span><br><span> VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);</span><br><span> VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span> VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span> VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);</span><br><span> VOID AcLossControl (IN UINT8 AcLossControlValue);</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c</span><br><span>index 37880b4..2c2b688 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c</span><br><span>@@ -192,69 +192,6 @@</span><br><span> return RomSigPtr;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** RwXhciIndReg - Reserved **/</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-RwXhciIndReg (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 Index,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 AndMask,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 OrMask,</span><br><span style="color: hsl(0, 100%, 40%);">- IN AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 RevReg;</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_ADDR PciAddress;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;</span><br><span style="color: hsl(0, 100%, 40%);">- RevReg = ~AndMask;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;</span><br><span style="color: hsl(0, 100%, 40%);">- RevReg = ~AndMask;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** RwXhci0IndReg - Reserved **/</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-RwXhci0IndReg (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 Index,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 AndMask,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 OrMask,</span><br><span style="color: hsl(0, 100%, 40%);">- IN AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 RevReg;</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_ADDR PciAddress;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;</span><br><span style="color: hsl(0, 100%, 40%);">- RevReg = ~AndMask;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** RwXhci1IndReg - Reserved **/</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-RwXhci1IndReg (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 Index,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 AndMask,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 OrMask,</span><br><span style="color: hsl(0, 100%, 40%);">- IN AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 RevReg;</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_ADDR PciAddress;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;</span><br><span style="color: hsl(0, 100%, 40%);">- RevReg = ~AndMask;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /** ReadXhci0Phy - Reserved **/</span><br><span> VOID</span><br><span> ReadXhci0Phy (</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c</span><br><span>index ae02aec..1df709c 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c</span><br><span>@@ -55,52 +55,6 @@</span><br><span> #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT)</span><br><span> /*----------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * ProgramPciByteTable - Program PCI register by table (8 bits data)</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] pPciByteTable - Table data pointer</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] dwTableSize - Table length</span><br><span style="color: hsl(0, 100%, 40%);">- * @param[in] StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-ProgramPciByteTable (</span><br><span style="color: hsl(0, 100%, 40%);">- IN REG8_MASK *pPciByteTable,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT16 dwTableSize,</span><br><span style="color: hsl(0, 100%, 40%);">- IN AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 i;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 dbBusNo;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 dbDevFnNo;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Or8;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Mask8;</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_ADDR PciAddress;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dbBusNo = pPciByteTable->RegIndex;</span><br><span style="color: hsl(0, 100%, 40%);">- dbDevFnNo = pPciByteTable->AndMask;</span><br><span style="color: hsl(0, 100%, 40%);">- pPciByteTable++;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for ( i = 1; i < dwTableSize; i++ ) {</span><br><span style="color: hsl(0, 100%, 40%);">- if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) {</span><br><span style="color: hsl(0, 100%, 40%);">- pPciByteTable++;</span><br><span style="color: hsl(0, 100%, 40%);">- dbBusNo = pPciByteTable->RegIndex;</span><br><span style="color: hsl(0, 100%, 40%);">- dbDevFnNo = pPciByteTable->AndMask;</span><br><span style="color: hsl(0, 100%, 40%);">- pPciByteTable++;</span><br><span style="color: hsl(0, 100%, 40%);">- i++;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex;</span><br><span style="color: hsl(0, 100%, 40%);">- Or8 = pPciByteTable->OrMask;</span><br><span style="color: hsl(0, 100%, 40%);">- Mask8 = ~pPciByteTable->AndMask;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- pPciByteTable++;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*----------------------------------------------------------------------------------------*/</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span> * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data)</span><br><span> *</span><br><span> *</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c</span><br><span>index 7c55c4e..136353e 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c</span><br><span>@@ -72,22 +72,3 @@</span><br><span> LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-VOID</span><br><span style="color: hsl(0, 100%, 40%);">-RwPci (</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 Address,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT8 OpFlag,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 Mask,</span><br><span style="color: hsl(0, 100%, 40%);">- IN UINT32 Data,</span><br><span style="color: hsl(0, 100%, 40%);">- IN AMD_CONFIG_PARAMS *StdHeader</span><br><span style="color: hsl(0, 100%, 40%);">- )</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_ADDR PciAddress;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 rMask;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);</span><br><span style="color: hsl(0, 100%, 40%);">- rMask = ~Mask;</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28082">change 28082</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28082"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb </div>
<div style="display:none"> Gerrit-Change-Number: 28082 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>