<p>Kane Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28074">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Disable usb2 phy power gating.<br><br>Currently, we found the usb2 phy registers value are restored to soc<br>default after xhci PS3, PS0 are executed.<br>This will cause some usb 2.0 devices not detected after xhci resumes<br>from D3.<br><br>Before root cause, this patch temporarily disables the usb2 phy power<br>gating in xhci PS0 PS3 so that usb2phy registers won't be restored to<br>soc default.<br><br>BUG=b:110175562<br>TEST=check usb2 phy registers are not gone.<br><br>Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d<br>Signed-off-by: Kane Chen <kane.chen@intel.com><br>---<br>M src/soc/intel/skylake/acpi/xhci.asl<br>1 file changed, 0 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28074/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl</span><br><span>index 29367de..926f6ac 100644</span><br><span>--- a/src/soc/intel/skylake/acpi/xhci.asl</span><br><span>+++ b/src/soc/intel/skylake/acpi/xhci.asl</span><br><span>@@ -149,24 +149,6 @@</span><br><span> </span><br><span> /* Disable USB2 PHY SUS Well Power Gating */</span><br><span> Store (Zero, ^UPSW)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Apply USB2 PHPY Power Gating workaround if needed.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- If (^^PMC.UWAB) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write to MTPMC to have PMC disable power gating */</span><br><span style="color: hsl(0, 100%, 40%);">- Store (1, ^^PMC.MPMC)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- Store (10, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- While (^^PMC.PMFS) {</span><br><span style="color: hsl(0, 100%, 40%);">- If (LNot (Local0)) {</span><br><span style="color: hsl(0, 100%, 40%);">- Break</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- Decrement (Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- Sleep (10)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> }</span><br><span> </span><br><span> Method (_PS3, 0, Serialized)</span><br><span>@@ -202,26 +184,6 @@</span><br><span> Store (3, Local0)</span><br><span> Store (Local0, ^D0D3)</span><br><span> Store (^D0D3, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Apply USB2 PHPY Power Gating workaround if needed.</span><br><span style="color: hsl(0, 100%, 40%);">- * This code assumes XDCI is disabled, if it is enabled</span><br><span style="color: hsl(0, 100%, 40%);">- * then this must also check if it is in D3 state too.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- If (^^PMC.UWAB) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write to MTPMC to have PMC enable power gating */</span><br><span style="color: hsl(0, 100%, 40%);">- Store (3, ^^PMC.MPMC)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- Store (10, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- While (^^PMC.PMFS) {</span><br><span style="color: hsl(0, 100%, 40%);">- If (LNot (Local0)) {</span><br><span style="color: hsl(0, 100%, 40%);">- Break</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- Decrement (Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- Sleep (10)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> }</span><br><span> </span><br><span> /* Root Hub for Skylake-LP PCH */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28074">change 28074</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d </div>
<div style="display:none"> Gerrit-Change-Number: 28074 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kane Chen <kane.chen@intel.com> </div>