<p>Matt Delco has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28068">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block/cpu: add function to init cppc_config<br><br>This change adds a method to init a cppc_config structure in a way that<br>should ideally work across Intel processors that support EIST.<br><br>Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1<br>Signed-off-by: Matt Delco <delco@chromium.org><br>---<br>M src/soc/intel/common/block/cpu/cpulib.c<br>M src/soc/intel/common/block/include/intelblocks/cpulib.h<br>2 files changed, 187 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28068/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>index 112a049..9191fd5 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>+++ b/src/soc/intel/common/block/cpu/cpulib.c</span><br><span>@@ -216,6 +216,185 @@</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Init cppc_config in a way that's appropriate for Intel</span><br><span style="color: hsl(120, 100%, 40%);">+ * processors with Intel Enhanced Speed Step Technology.</span><br><span style="color: hsl(120, 100%, 40%);">+ * NOTE: version 2 is expected to be the typical use case.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For now this function 'punts' on version 3 and just</span><br><span style="color: hsl(120, 100%, 40%);">+ * populates the additional fields with 'unsupported'.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void cpu_init_cppc_config(struct cppc_config *config, u32 version)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_addr_t msr = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .space_id = ACPI_ADDRESS_SPACE_FIXED,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_width = 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_offset = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .access_size = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrl = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrh = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ static const acpi_addr_t unsupported = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .space_id = ACPI_ADDRESS_SPACE_MEMORY,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_width = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bit_offset = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .resv = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrl = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .addrh = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config->version = version;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = MSR_HWP_CAPABILITIES;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Highest Performance:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_HIGHEST_PERF] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Nominal Performance -> Guaranteed Performance:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_NOMINAL_PERF] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lowest Nonlinear Performance -> Most Efficient Performance:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_LOWEST_NONL_PERF] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Lowest Performance:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 24;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_LOWEST_PERF] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Guaranteed Performance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_GUARANTEED_PERF] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = MSR_HWP_REQUEST;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Desired Performance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_DESIRED_PERF] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Minimum Performance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_MIN_PERF] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Maximum Performance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_MAX_PERF] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Performance Reduction Tolerance Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Time Window Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_TIME_WINDOW] = unsupported;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Counter Wraparound Time:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_COUNTER_WRAP] = unsupported;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = MSR_MPERF;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Reference Performance Counter Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_width = 64;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_REF_PERF_COUNTER] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = MSR_APERF;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Delivered Performance Counter Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = MSR_HWP_STATUS;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Performance Limited Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_width = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_PERF_LIMITED] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = MSR_PM_ENABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPPC Enable Register:</span><br><span style="color: hsl(120, 100%, 40%);">+ * ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)},</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_ENABLE] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (version >= 2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Autonomous Selection Enable is populated below */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Autonomous Activity Window Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Energy Performance Preference Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_PERF_PREF] = unsupported;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reference Performance */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_REF_PERF] = unsupported;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (version >= 3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lowest Frequency */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_LOWEST_FREQ] = unsupported;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Nominal Frequency */</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_NOMINAL_FREQ] = unsupported;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Autonomous Selection Enable = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field is actually the first addition in version 2 but</span><br><span style="color: hsl(120, 100%, 40%);">+ * it's so unlike the others I'm populating it last.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.space_id = ACPI_ADDRESS_SPACE_MEMORY;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_width = 32;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.access_size = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ config->regs[CPPC_AUTO_SELECT] = msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span> * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120</span><br><span> * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.</span><br><span> */</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h</span><br><span>index 88f04b4..0071033 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h</span><br><span>@@ -109,6 +109,14 @@</span><br><span> void cpu_disable_eist(void);</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Init CPPC block with MSRs for Intel Enhanced Speed Step Technology.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Version 2 is suggested--this function's implementation of version 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * may have room for improvment.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+struct cppc_config;</span><br><span style="color: hsl(120, 100%, 40%);">+void cpu_init_cppc_config(struct cppc_config *config, u32 version);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span> * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120</span><br><span> * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.</span><br><span> */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28068">change 28068</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28068"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 </div>
<div style="display:none"> Gerrit-Change-Number: 28068 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt Delco <delco@chromium.org> </div>