<p>Matt Delco has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28067">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: add more msr defines<br><br>This change adds some MSRs that are needed in a subsequent change to add<br>support for Continuous Performance Control.<br><br>Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296<br>Signed-off-by: Matt Delco <delco@chromium.org><br>---<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>1 file changed, 6 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28067/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index e1fc431..e588434 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -37,6 +37,8 @@</span><br><span> #define MSR_BIOS_UPGD_TRIG   0x7a</span><br><span> #define  SGX_ACTIVATE_BIT       (1)</span><br><span> #define MSR_PMG_IO_CAPTURE_BASE  0xe4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_MPERF         0xe7</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_APERF         0xe8</span><br><span> #define MSR_POWER_MISC          0x120</span><br><span> #define   ENABLE_IA_UNTRUSTED  (1 << 6)</span><br><span> #define   FLUSH_DL1_L2                (1 << 8)</span><br><span>@@ -118,6 +120,10 @@</span><br><span> #define PKG_POWER_LIMIT_TIME_MASK      (0x7f)</span><br><span> #define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24</span><br><span> #define PKG_POWER_LIMIT_DUTYCYCLE_MASK  (0x7f)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PM_ENABLE                   0x770</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_HWP_CAPABILITIES             0x771</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_HWP_REQUEST                  0x774</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_HWP_STATUS                   0x770</span><br><span> /* SMM save state MSRs */</span><br><span> #define SMBASE_MSR                        0xc20</span><br><span> #define IEDBASE_MSR                    0xc22</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28067">change 28067</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28067"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 </div>
<div style="display:none"> Gerrit-Change-Number: 28067 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt Delco <delco@chromium.org> </div>