<p>Angel Pons has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28056">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/hp/630: Add new mainboard (NOT WORKING)<br><br>This is a Nehalem laptop with an ITE IT8518E EC. I<br>have managed to reach the payload stage, but SeaBIOS<br>hangs. EC support is completely missing.<br><br>Working: Reaching the payload, internal display.<br>Not working: Everything else after what works.<br><br>Change-Id: Ic9bf4bedb0724110965f2e22b2515cbbc5ed47c7<br>Signed-off-by: Angel Pons <th3fanbus@gmail.com><br>---<br>A src/mainboard/hp/630/Kconfig<br>A src/mainboard/hp/630/Kconfig.name<br>A src/mainboard/hp/630/Makefile.inc<br>A src/mainboard/hp/630/acpi/ec.asl<br>A src/mainboard/hp/630/acpi/platform.asl<br>A src/mainboard/hp/630/acpi/superio.asl<br>A src/mainboard/hp/630/acpi_tables.c<br>A src/mainboard/hp/630/board_info.txt<br>A src/mainboard/hp/630/cmos.default<br>A src/mainboard/hp/630/cmos.layout<br>A src/mainboard/hp/630/devicetree.cb<br>A src/mainboard/hp/630/dsdt.asl<br>A src/mainboard/hp/630/gma-mainboard.ads<br>A src/mainboard/hp/630/gpio.c<br>A src/mainboard/hp/630/hda_verb.c<br>A src/mainboard/hp/630/mainboard.c<br>A src/mainboard/hp/630/romstage.c<br>17 files changed, 1,184 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28056/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/hp/630/Kconfig b/src/mainboard/hp/630/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..163aeff</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/Kconfig</span><br><span>@@ -0,0 +1,37 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_HP_630</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_NEHALEM</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_IBEXPEAK</span><br><span style="color: hsl(120, 100%, 40%);">+ select NO_UART_ON_SUPERIO</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_4096</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_INT15</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LIBGFXINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ #select INTEL_GMA_HAVE_VBT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default hp/630</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "630"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config USBDEBUG_HCD_INDEX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xe0000000</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/hp/630/Kconfig.name b/src/mainboard/hp/630/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..bb7e097</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_HP_630</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "630 Notebook PC"</span><br><span>diff --git a/src/mainboard/hp/630/Makefile.inc b/src/mainboard/hp/630/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..7088731</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/Makefile.inc</span><br><span>@@ -0,0 +1,18 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads</span><br><span>diff --git a/src/mainboard/hp/630/acpi/ec.asl b/src/mainboard/hp/630/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..8b13789</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/acpi/ec.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/hp/630/acpi/platform.asl b/src/mainboard/hp/630/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..893d224</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/acpi/platform.asl</span><br><span>@@ -0,0 +1,144 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* These come from the dynamically created CPU SSDT */</span><br><span style="color: hsl(120, 100%, 40%);">+External(PDC0)</span><br><span style="color: hsl(120, 100%, 40%);">+External(PDC1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The APM port can be used for generating software SMIs */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+OperationRegion (APMP, SystemIO, 0xb2, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+Field (APMP, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ APMC, 8, /* APM command */</span><br><span style="color: hsl(120, 100%, 40%);">+ APMS, 8 /* APM status */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMI I/O Trap */</span><br><span style="color: hsl(120, 100%, 40%);">+Method(TRAP, 1, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (Arg0, SMIF) /* SMI Function */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, TRP0) /* Generate trap */</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (SMIF) /* Return value of SMI handler */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The _PIC method is called by the OS to choose between interrupt</span><br><span style="color: hsl(120, 100%, 40%);">+ * routing via the i8259 interrupt controller or the APIC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * _PIC is called with a parameter of 0 for i8259 configuration and</span><br><span style="color: hsl(120, 100%, 40%);">+ * with a parameter of 1 for Local Apic/IOAPIC configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PIC, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Remember the OS' IRQ routing choice. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store(Arg0, PICM)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The _PTS method (Prepare To Sleep) is called before the OS is</span><br><span style="color: hsl(120, 100%, 40%);">+ * entering a sleep state. The sleep state number is passed in Arg0</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* The _WAK method is called on system wakeup */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(Package(){0,0})</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(UCMS, 1, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* System Bus */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Scope(\_SB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* This method is placed on the top level, so we can make sure it's the</span><br><span style="color: hsl(120, 100%, 40%);">+ * first executed _INI method.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method(_INI, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The DTS data in NVS is probably not up to date.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Update temperature values and make sure AP thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ * interrupts can happen</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TRAP(71) */ /* TODO */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Determine the Operating System and save the value in OSYS.</span><br><span style="color: hsl(120, 100%, 40%);">+ * We have to do this in order to be able to work around</span><br><span style="color: hsl(120, 100%, 40%);">+ * certain windows bugs.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * OSYS value | Operating System</span><br><span style="color: hsl(120, 100%, 40%);">+ * -----------+------------------</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2000 | Windows 2000</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2001 | Windows XP(+SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2002 | Windows XP SP2</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2006 | Windows Vista</span><br><span style="color: hsl(120, 100%, 40%);">+ * ???? | Windows 7</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Let's assume we're running at least Windows 2000 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2000, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (CondRefOf(_OSI)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2001")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2001, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2001 SP1")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2001, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2001 SP2")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2002, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2001.1")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2001, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2001.1 SP1")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2001, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2006")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2006, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2006.1")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2006, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2006 SP1")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2006, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2009")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2009, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ If (_OSI("Windows 2012")) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (2012, OSYS)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/630/acpi/superio.asl b/src/mainboard/hp/630/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..f2b35ba</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/acpi/superio.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/pc80/pc/ps2_controller.asl></span><br><span>diff --git a/src/mainboard/hp/630/acpi_tables.c b/src/mainboard/hp/630/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0914299</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/acpi_tables.c</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/ibexpeak/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set thermal levels */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tcrt = 100;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tpsv = 90;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/630/board_info.txt b/src/mainboard/hp/630/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..689ca8f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/board_info.txt</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: laptop</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: n</span><br><span>diff --git a/src/mainboard/hp/630/cmos.default b/src/mainboard/hp/630/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..38f2bd3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/cmos.default</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Debug</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+sata_mode=AHCI</span><br><span>diff --git a/src/mainboard/hp/630/cmos.layout b/src/mainboard/hp/630/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..fad1868</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/cmos.layout</span><br><span>@@ -0,0 +1,125 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2013 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 2 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#400 8 r 0 reserved for century byte</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: EC</span><br><span style="color: hsl(120, 100%, 40%);">+#411 1 e 8 first_battery</span><br><span style="color: hsl(120, 100%, 40%);">+#412 1 e 1 bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+#413 1 e 1 wwan</span><br><span style="color: hsl(120, 100%, 40%);">+#414 1 e 1 touchpad</span><br><span style="color: hsl(120, 100%, 40%);">+#415 1 e 1 wlan</span><br><span style="color: hsl(120, 100%, 40%);">+#416 1 e 1 trackpoint</span><br><span style="color: hsl(120, 100%, 40%);">+#417 1 e 1 fn_ctrl_swap</span><br><span style="color: hsl(120, 100%, 40%);">+#418 1 e 1 sticky_fn</span><br><span style="color: hsl(120, 100%, 40%);">+#419 1 e 1 power_management_beeps</span><br><span style="color: hsl(120, 100%, 40%);">+#420 1 e 1 low_battery_beep</span><br><span style="color: hsl(120, 100%, 40%);">+#421 1 e 9 sata_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#422 1 e 11 usb_always_on</span><br><span style="color: hsl(120, 100%, 40%);">+#423 1 r 1 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+424 3 e 10 gfx_uma_size</span><br><span style="color: hsl(120, 100%, 40%);">+#427 5 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+432 8 h 0 volume</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+#1000 24 r 0 amd_reserved</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+8 0 Secondary</span><br><span style="color: hsl(120, 100%, 40%);">+8 1 Primary</span><br><span style="color: hsl(120, 100%, 40%);">+9 0 AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+9 1 Compatible</span><br><span style="color: hsl(120, 100%, 40%);">+10 0 32M</span><br><span style="color: hsl(120, 100%, 40%);">+10 1 48M</span><br><span style="color: hsl(120, 100%, 40%);">+10 2 64M</span><br><span style="color: hsl(120, 100%, 40%);">+10 3 128M</span><br><span style="color: hsl(120, 100%, 40%);">+10 5 96M</span><br><span style="color: hsl(120, 100%, 40%);">+10 6 160M</span><br><span style="color: hsl(120, 100%, 40%);">+11 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+11 1 AC and battery</span><br><span style="color: hsl(120, 100%, 40%);">+11 2 AC only</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 447 984</span><br><span>diff --git a/src/mainboard/hp/630/devicetree.cb b/src/mainboard/hp/630/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..f782f6c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/devicetree.cb</span><br><span>@@ -0,0 +1,90 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+## modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+## published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+## the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/nehalem</span><br><span style="color: hsl(120, 100%, 40%);">+ # IGD Displays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.ndid" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DisplayPort Hotplug with 6ms pulse</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "gpu_dp_d_hotplug" = "0x06"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Panel as LVDS and configure power delays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_port_select" = "0" # LVDS</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_cycle_delay" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_up_delay" = "250"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_down_delay" = "250"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_on_delay" = "2500"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_off_delay" = "2500"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_cpu_backlight" = "0x58d"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_pch_backlight" = "0x061a061a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.use_spread_spectrum_clock" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.link_frequency_270_mhz" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_2065x</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pci_mmio_size" = "2048"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/ibexpeak</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPI routing</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0 No effect (default)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 2 SCI (if corresponding GPIO_EN bit is also set)</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "gpi1_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "gpi13_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x03"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "gpe0_en" = "0x20022046"</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "alt_gp_smi_en" = "0x0000"</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "gen1_dec" = "0x7c1601"</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "gen2_dec" = "0x0c15e1"</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "gen3_dec" = "0x1c1681"</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "gen4_dec" = "0x040069"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "p_cnt_throttling_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ #register "c2_latency" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # HECI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 on end # IDE/SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # USB2 EHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # Audio Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on end # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on end # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # USB2 EHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # PCI-LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # IDE/SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 on end # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/hp/630/dsdt.asl b/src/mainboard/hp/630/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..681c655</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/dsdt.asl</span><br><span>@@ -0,0 +1,84 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, /* DSDT revision: ACPI v3.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", /* OEM id */</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", /* OEM table id */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20130325 /* OEM revision */</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Some generic macros */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* global NVS and variables */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/model_206ax/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/nehalem/acpi/nehalem.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (UNCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_BBN, 0xFF)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId ("PNP0A03"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_CRS, ResourceTemplate ()</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000, /* Granularity */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00FF, /* Range Minimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00FF, /* Range Maximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000, /* Translation Offset */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0001, /* Length */</span><br><span style="color: hsl(120, 100%, 40%);">+ ,, )</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (SAD)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x01)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (RID, 0x00)</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (SADC, PCI_Config, 0x00, 0x0100)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (SADC, DWordAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x40),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM0, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM1, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM2, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM3, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM4, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM5, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM6, 8</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/630/gma-mainboard.ads b/src/mainboard/hp/630/gma-mainboard.ads</span><br><span>new file mode 100644</span><br><span>index 0000000..4e9cf2a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/gma-mainboard.ads</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+-- it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+-- the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+-- (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+-- but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+-- GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+private package GMA.Mainboard is</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ports : constant Port_List :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (HDMI1,</span><br><span style="color: hsl(120, 100%, 40%);">+ HDMI2,</span><br><span style="color: hsl(120, 100%, 40%);">+ HDMI3,</span><br><span style="color: hsl(120, 100%, 40%);">+ Analog,</span><br><span style="color: hsl(120, 100%, 40%);">+ Internal,</span><br><span style="color: hsl(120, 100%, 40%);">+ others => Disabled);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+end GMA.Mainboard;</span><br><span>diff --git a/src/mainboard/hp/630/gpio.c b/src/mainboard/hp/630/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..89ae9c0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/gpio.c</span><br><span>@@ -0,0 +1,225 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio58 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio63 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio75 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/hp/630/hda_verb.c b/src/mainboard/hp/630/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..4d6497c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/hda_verb.c</span><br><span>@@ -0,0 +1,76 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0270, /* Codec Vendor / Device ID: Realtek */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x103c3674, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000000b, /* Number of 4 dword sets */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x0, 0x103c3674),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x12. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x12, 0x99a30930),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x14. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x14, 0x99130110),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x17. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x18. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11820),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x19. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1a. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1b. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1d. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1d, 0x40179a2d),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1e. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x21. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x80862804, /* Codec Vendor / Device ID: Intel */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x103c3674, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000004, /* Number of 4 dword sets */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x3, 0x103c3674),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x04. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x04, 0x58560010),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x05. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x05, 0x58560020),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x06. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560010),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/hp/630/mainboard.c b/src/mainboard/hp/630/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..f6732cf</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/mainboard.c</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/int15.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_PANEL_FIT_DEFAULT,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 2);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/hp/630/romstage.c b/src/mainboard/hp/630/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..edb7a9c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/630/romstage.c</span><br><span>@@ -0,0 +1,283 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/bist.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/ibexpeak/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/nehalem/nehalem.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/nehalem/raminit.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/ibexpeak/me.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* X201 EC Decode Range Port60/64, Port62/66 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable EC, PS/2 Keyboard/Mouse */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_EN,</span><br><span style="color: hsl(120, 100%, 40%);">+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |</span><br><span style="color: hsl(120, 100%, 40%);">+ COMA_LPC_EN | GAMEL_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, ETR3,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);*/</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ southbridge_configure_default_intmap();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if 0</span><br><span style="color: hsl(120, 100%, 40%);">+ static const u32 rcba_dump3[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(4 * i + 0x3310) = rcba_dump3[i];</span><br><span style="color: hsl(120, 100%, 40%);">+ (void)RCBA32(4 * i + 0x3310);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void write_acpi32(u32 addr, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(val, DEFAULT_PMBASE | addr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void write_acpi16(u32 addr, u16 val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ outw(val, DEFAULT_PMBASE | addr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static inline u32 read_acpi32(u32 addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return inl(DEFAULT_PMBASE | addr);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_fsb_frequency(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 block[5];</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 fsbfreq = 62879;</span><br><span style="color: hsl(120, 100%, 40%);">+ smbus_block_read(0x69, 0, 5, block);</span><br><span style="color: hsl(120, 100%, 40%);">+ block[0] = fsbfreq;</span><br><span style="color: hsl(120, 100%, 40%);">+ block[1] = fsbfreq >> 8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smbus_block_write(0x69, 0, 5, block);</span><br><span style="color: hsl(120, 100%, 40%);">+}*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_romstage_entry(unsigned long bist)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ int s3resume = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_init(timestamp_get());</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_START_ROMSTAGE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (bist == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_lapic();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nehalem_early_initialization(NEHALEM_MOBILE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable USB Power. We need to do it early for usbdebug to work. */</span><br><span style="color: hsl(120, 100%, 40%);">+ //ec_set_bit(0x3b, 4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable GPIOs */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_pch_gpios(&mainboard_gpio_map);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* This should probably go away. Until now it is required</span><br><span style="color: hsl(120, 100%, 40%);">+ * and mainboard specific</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ rcba_config();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Halt if there was a built in self test failure */</span><br><span style="color: hsl(120, 100%, 40%);">+ report_bist_failure(bist);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read PM1_CNT */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = inl(DEFAULT_PMBASE + 0x04);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (((reg32 >> 10) & 7) == 5) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "a2: %02x\n", reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(reg8 & 0x20)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (acpi_s3_resume_allowed()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ s3resume = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "Resume from S3 detected, but disabled.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable SMBUS. */</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_smbus();</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEFAULT_GPIOBASE | 0x3a);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x50, 0x15ec);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(inb(0x15ee) & 0x70, 0x15ee);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ write_acpi16(0x2, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_acpi32(0x28, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_acpi32(0x2c, 0x0);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!s3resume) {</span><br><span style="color: hsl(120, 100%, 40%);">+ read_acpi32(0x4);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_acpi32(0x20);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_acpi32(0x34);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_acpi16(0x0, 0x900);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_acpi32(0x20, 0xffff7ffe);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_acpi32(0x34, 0x56974);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ }*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ early_thermal_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_BEFORE_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chipset_init(s3resume);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ //set_fsb_frequency();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ raminit(s3resume, spd_addrmap);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timestamp_add_now(TS_AFTER_INITRAM);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_early_me_status();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (s3resume) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear SLP_TYPE. This will break stage2 but</span><br><span style="color: hsl(120, 100%, 40%);">+ * we care for that when we get there.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = inl(DEFAULT_PMBASE + 0x04);</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ romstage_handoff_init(s3resume);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!s3resume)</span><br><span style="color: hsl(120, 100%, 40%);">+ quick_ram_check();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28056">change 28056</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28056"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic9bf4bedb0724110965f2e22b2515cbbc5ed47c7 </div>
<div style="display:none"> Gerrit-Change-Number: 28056 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> </div>