<p>Philipp Deppenwiese has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28024">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/opencellular/elgon: Add mainboard support<br><br>Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5<br>Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org><br>---<br>A src/mainboard/opencellular/elgon/Kconfig<br>A src/mainboard/opencellular/elgon/Kconfig.name<br>A src/mainboard/opencellular/elgon/Makefile.inc<br>A src/mainboard/opencellular/elgon/bdk_devicetree.c<br>A src/mainboard/opencellular/elgon/board.fmd<br>A src/mainboard/opencellular/elgon/board_info.txt<br>A src/mainboard/opencellular/elgon/bootblock.c<br>A src/mainboard/opencellular/elgon/death.c<br>A src/mainboard/opencellular/elgon/devicetree.cb<br>A src/mainboard/opencellular/elgon/gbcv2.dts<br>A src/mainboard/opencellular/elgon/mainboard.c<br>A src/mainboard/opencellular/elgon/mainboard.h<br>A src/mainboard/opencellular/elgon/memlayout.ld<br>A src/mainboard/opencellular/elgon/romstage.c<br>A src/mainboard/opencellular/elgon/vboot.fmd<br>15 files changed, 1,259 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28024/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/opencellular/elgon/Kconfig b/src/mainboard/opencellular/elgon/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..bd35e9c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/Kconfig</span><br><span>@@ -0,0 +1,94 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright 2018 Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_OPENCELLULAR_ELGON</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select COMMON_CBFS_SPI_WRAPPER</span><br><span style="color: hsl(120, 100%, 40%);">+ select RTC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_CAVIUM_CN81XX</span><br><span style="color: hsl(120, 100%, 40%);">+ select SPI_FLASH</span><br><span style="color: hsl(120, 100%, 40%);">+ select SPI_FLASH_WINBOND</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_I2C_TPM_GENERIC</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_TPM1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_NO_BOARD_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_DISABLE_LID_SHUTDOWN</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_DISABLE_FWMP</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config GBB_HWID</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ELGON"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "opencellular/elgon"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Open Cellular"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRIVER_TPM_I2C_BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRIVER_TPM_I2C_ADDR</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRAM_SIZE_MB</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4096</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOOT_DEVICE_SPI_FLASH_BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CONSOLE_SERIAL_UART_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on DRIVERS_UART</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x87E028000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config UART_FOR_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on DRIVERS_UART</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config FMDFILE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot.fmd" if VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ default 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+##########################################################</span><br><span style="color: hsl(120, 100%, 40%);">+#### Update below when adding a new derivative board. ####</span><br><span style="color: hsl(120, 100%, 40%);">+##########################################################</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "devicetree.cb"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Elgon"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/opencellular/elgon/Kconfig.name b/src/mainboard/opencellular/elgon/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..e0c4290</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_OPENCELLULAR_ELGON</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Elgon"</span><br><span>diff --git a/src/mainboard/opencellular/elgon/Makefile.inc b/src/mainboard/opencellular/elgon/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..26de1cc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/Makefile.inc</span><br><span>@@ -0,0 +1,41 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += death.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += bdk_devicetree.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += death.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += mainboard.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += bdk_devicetree.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += death.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += death.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+MB_DIR = src/mainboard/$(MAINBOARDDIR)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+LINUX_DTB = gbcv2.dtb</span><br><span style="color: hsl(120, 100%, 40%);">+build/$(LINUX_DTB):</span><br><span style="color: hsl(120, 100%, 40%);">+ dtc -p 4096 -I dts -O dtb -o build/$(LINUX_DTB) -i $(MB_DIR) $(MB_DIR)/$(patsubst %.dtb,%.dts,$(LINUX_DTB))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+cbfs-files-y += $(LINUX_DTB)</span><br><span style="color: hsl(120, 100%, 40%);">+$(LINUX_DTB)-file := build/$(LINUX_DTB)</span><br><span style="color: hsl(120, 100%, 40%);">+$(LINUX_DTB)-type := raw</span><br><span>diff --git a/src/mainboard/opencellular/elgon/bdk_devicetree.c b/src/mainboard/opencellular/elgon/bdk_devicetree.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9f8c64e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/bdk_devicetree.c</span><br><span>@@ -0,0 +1,106 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// This file is automatically generated.</span><br><span style="color: hsl(120, 100%, 40%);">+// DO NOT EDIT BY HAND.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bdk-devicetree.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct bdk_devicetree_key_value devtree[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-DQX-CTL", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-WR.RANKS4", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2", "0x4"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0", "0x5"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2", "0x5"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0", "0x6"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1", "0x6"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0", "0x22"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0", "0x1f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2", "0x1f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0", "0x19"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1", "0x19"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2", "0x19"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0", "0x1f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1", "0x1f"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2", "0x3"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1", "0x3"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2", "0x4080102"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1", "0x1010202"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MIN-RODT-CTL", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MAX-RODT-CTL", "0x7"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-OFFSET-EN", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-OFFSET", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-DDR2T", "0x1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-CUSTOM-FPRCH2", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX0.P0", "0x00001000"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"PHY-ADDRESS.N0.BGX2.P0", "0x00001000"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX0.P0", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX0.P1", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX0.P2", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX0.P3", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX1.P0", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX1.P1", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BGX-ENABLE.N0.BGX2.P0", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-NUM-PACKET-BUFFERS", "0x1000"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-PACKET-BUFFER-SIZE", "0x400"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-SHOW-LINK-STATUS", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-COREMASK", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-BOOT-MENU-TIMEOUT", "0x05"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-BOOT-PATH-OPTION", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"BDK-CONFIG-TRACE", "1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"MULTI-NODE", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-AUTO-CONFIG", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-DIP-AUTO-CONFIG", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-MODE.N0.QLM0", "PCIE_1X1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-MODE.N0.QLM1", "SGMII_2X1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-MODE.N0.QLM2", "PCIE_1X2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-MODE.N0.QLM3", "SATA_2X1"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-FREQ.N0.QLM0", "6000"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-FREQ.N0.QLM1", "1250"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-FREQ.N0.QLM2", "6000"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-FREQ.N0.QLM3", "6000"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-CLK.N0.QLM0", "2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-CLK.N0.QLM1", "2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-CLK.N0.QLM2", "2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"QLM-CLK.N0.QLM3", "2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-SPEED.N0", "1600"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0", "0x1050"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"USB-REFCLK-SRC.N0.PORT0", "0"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO45", "0x2"},</span><br><span style="color: hsl(120, 100%, 40%);">+{"GPIO-PIN-SELECT-GPIO46", "0x250"},</span><br><span style="color: hsl(120, 100%, 40%);">+{0, 0},</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/opencellular/elgon/board.fmd b/src/mainboard/opencellular/elgon/board.fmd</span><br><span>new file mode 100644</span><br><span>index 0000000..fb0bf13</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/board.fmd</span><br><span>@@ -0,0 +1,12 @@</span><br><span style="color: hsl(120, 100%, 40%);">+FLASH@0x0 16M {</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0x0 0x1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_SECTION@0x0 0x1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ # bootblock includes trusted/non-trusted CLIB, CSIB,</span><br><span style="color: hsl(120, 100%, 40%);">+ # and BL1FWs packaged in</span><br><span style="color: hsl(120, 100%, 40%);">+ # src/soc/cavium/common/Makefile.inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOTBLOCK@0x10000 0x70000</span><br><span style="color: hsl(120, 100%, 40%);">+ FMAP@0x80000 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT(CBFS)@0x81000 0xf7f000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/opencellular/elgon/board_info.txt b/src/mainboard/opencellular/elgon/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..06dcd35</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Vendor name: Open Cellular</span><br><span style="color: hsl(120, 100%, 40%);">+Board name: Elgon</span><br><span style="color: hsl(120, 100%, 40%);">+Category: sbc</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span>diff --git a/src/mainboard/opencellular/elgon/bootblock.c b/src/mainboard/opencellular/elgon/bootblock.c</span><br><span>new file mode 100644</span><br><span>index 0000000..21cc6b2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/bootblock.c</span><br><span>@@ -0,0 +1,55 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootblock_common.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/soc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/uart.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "mainboard.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_mainboard_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Route UART0 to CON1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(ELGON_GPIO_UART_SEL, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Turn off error LED */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(ELGON_GPIO_ERROR_LED, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE))</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void configure_spi_flash(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: Only tested on EM100 Pro */</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_init_custom(0, // bus</span><br><span style="color: hsl(120, 100%, 40%);">+ 12500000, // speed Hz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // idle low disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // zero idle cycles between transfers</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // MSB first</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, // Chip select 0</span><br><span style="color: hsl(120, 100%, 40%);">+ 1); // assert is high</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Route SPI to SoC */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(ELGON_GPIO_SPI_MUX, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_mainboard_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_spi_flash();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/opencellular/elgon/death.c b/src/mainboard/opencellular/elgon/death.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d1b1988</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/death.c</span><br><span>@@ -0,0 +1,32 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "mainboard.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void die_notify(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 rate = 1000 / 5; // blink at 5 Hz</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(ELGON_GPIO_ERROR_LED, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ mdelay(rate);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_output(ELGON_GPIO_ERROR_LED, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ mdelay(rate);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/opencellular/elgon/devicetree.cb b/src/mainboard/opencellular/elgon/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..07d508a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/devicetree.cb</span><br><span>@@ -0,0 +1,210 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/cavium/cn81xx</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # MRML</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.1 on end # RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.2 on end # DAP</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.3 on end # MDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.4 on end # FUSE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.2 on end # SGPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.3 on end # SMI</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.4 on end # MMC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.5 on end # KEY</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.6 on end # BOOT BUS</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.7 on end # PBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # XCV</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 06.0 on end # L2C-TAD</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 07.0 on end # L2C-CBC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 07.4 on end # L2C-MCI</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.0 on end # UUA0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.1 on end # UUA1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.2 off end # UUA2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.3 off end # UUA3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.4 on end # VRM</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 09.0 on end # I2C0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 09.1 on end # I2C1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0a.0 on end # PCC Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0b.0 on end # IOBN</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0c.0 on end # OCLA0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0c.1 on end # OCLA1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.0 on end # PCIe0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.1 on end # PCIe1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.2 on end # PCIe2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.0 on end # bgx0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.1 off end # bgx1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # rgx0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # MAC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # GSER0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # GSER1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on end # GSER2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on end # GSER3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end #SMMU</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 on end #GIC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip soc/cavium/common/pci</span><br><span style="color: hsl(120, 100%, 40%);">+ register "secure" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 04.0 on end #GTI</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 05.0 on end # NIC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 06.0 on end # GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 07.0 on end # SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 08.0 on end # MIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 09.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0a.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0b.0 on end # NFC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0c.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0d.0 on end # PCM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0e.0 on end # VRM</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 0f.0 on end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.0 on end # USB0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 on end # USB1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # SATA0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA1</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/opencellular/elgon/gbcv2.dts b/src/mainboard/opencellular/elgon/gbcv2.dts</span><br><span>new file mode 100644</span><br><span>index 0000000..1f8a47b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/gbcv2.dts</span><br><span>@@ -0,0 +1,495 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/dts-v1/;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/ {</span><br><span style="color: hsl(120, 100%, 40%);">+ model = "Cavium ThunderX CN81XX board";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-81xx";</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-parent = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ psci {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,psci-0.2";</span><br><span style="color: hsl(120, 100%, 40%);">+ method = "smc";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpus {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu-map {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cluster0 {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ core0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ core1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ core2 {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu = <0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ core3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu = <0x5>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "cpu";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder", "arm,armv8";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-method = "psci";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ next-level-cache = <0x6>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu@1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "cpu";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder", "arm,armv8";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-method = "psci";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ next-level-cache = <0x6>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu@2 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "cpu";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder", "arm,armv8";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-method = "psci";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ next-level-cache = <0x6>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu@3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "cpu";</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder", "arm,armv8";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-method = "psci";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ next-level-cache = <0x6>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x5>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x5>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ l2-cache0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cache";</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x6>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x6>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timer {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,armv8-timer";</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x1 0xd 0x4 0x1 0xe 0x4 0x1 0xb 0x4 0x1 0xa 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pmu {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x1 0x7 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmc_supply_3v3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "regulator-fixed";</span><br><span style="color: hsl(120, 100%, 40%);">+ regulator-name = "mmc_supply_3v3";</span><br><span style="color: hsl(120, 100%, 40%);">+ regulator-min-microvolt = <0x325aa0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ regulator-max-microvolt = <0x325aa0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio = <0x7 0x8 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ enable-active-high;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0xf>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0xf>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-controller@801000000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,gic-v3";</span><br><span style="color: hsl(120, 100%, 40%);">+ #interrupt-cells = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #redistributor-regions = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-controller;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8010 0x0 0x0 0x10000 0x8010 0x80000000 0x0 0x600000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x1 0x9 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gic-its@801000020000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,gic-v3-its";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8010 0x20000 0x0 0x200000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-controller;</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0xd>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0xd>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ soc@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "simple-bus";</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges;</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ refclkuaa {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "fixed-clock";</span><br><span style="color: hsl(120, 100%, 40%);">+ #clock-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-frequency = <0x6f3c900>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-output-names = "refclkuaa";</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x8>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x8>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sclk {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "fixed-clock";</span><br><span style="color: hsl(120, 100%, 40%);">+ #clock-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-frequency = <0x2faf0800>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-output-names = "sclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0xe>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0xe>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ serial@87e028000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,pl011", "arm,primecell";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x28000000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x0 0x5 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0x8>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-names = "apb_pclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ skip-init;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ serial@87e029000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,pl011", "arm,primecell";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x29000000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x0 0x6 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0x8>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-names = "apb_pclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ skip-init;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ serial@87e02a000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,pl011", "arm,primecell";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x2a000000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x0 0x7 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0x8>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-names = "apb_pclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ skip-init;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ serial@87e02b000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,pl011", "arm,primecell";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x2b000000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x0 0x8 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0x8>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-names = "apb_pclk";</span><br><span style="color: hsl(120, 100%, 40%);">+ skip-init;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ watch-dog@8440000a0000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "arm,sbsa-gwdt";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8440 0xa0000 0x0 0x1000 0x8440 0xb0000 0x0 0x1000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x0 0x9 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smmu0@830000000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,smmu-v2";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8300 0x0 0x0 0x2000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #global-interrupts = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupts = <0x0 0x44 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu-masters = <0x9 0x100 0xa 0x200 0xb 0x300 0xc 0x400>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci@848000000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "pci-host-ecam-generic";</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-parent = <0xd>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-map = <0x0 0xd 0x0 0x10000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-range = <0x0 0x1f>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #stream-id-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+ dma-coherent;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8480 0x0 0x0 0x2000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x3000000 0x8010 0x0 0x8010 0x0 0x80 0x0 0x3000000 0x8100 0x0 0x8100 0x0 0x80 0x0 0x3000000 0x8680 0x0 0x8680 0x0 0x160 0x28000000 0x3000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x0 0x94000000 0x3000000 0x8400 0x0 0x8400 0x0 0x10 0x0 0x3000000 0x8430 0x0 0x8430 0x0 0x2 0x0 0x3000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x1f 0x3a000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x9>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x9>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mrml-bridge0@1,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge";</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x3000000 0x87e0 0x0 0x3000000 0x87e0 0x0 0x10 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x800 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio-nexus@1,3 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-mdio-nexus";</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0xb00 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ assigned-addresses = <0x3000000 0x87e0 0x5000000 0x0 0x800000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x87e0 0x5000000 0x3000000 0x87e0 0x5000000 0x0 0x800000>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio0@87e005003800 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-mdio";</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x5003800 0x0 0x30>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mdio1@87e005003880 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-mdio";</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x87e0 0x5003880 0x0 0x30>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmc@1,4 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-mmc";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0xc00 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0xe>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mmc-slot@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "mmc-slot";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ vmmc-supply = <0xf>;</span><br><span style="color: hsl(120, 100%, 40%);">+ max-frequency = <0x18cba80>;</span><br><span style="color: hsl(120, 100%, 40%);">+ no-1-8-v;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-width = <0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ disable-wp;</span><br><span style="color: hsl(120, 100%, 40%);">+ broken-cd;</span><br><span style="color: hsl(120, 100%, 40%);">+ sd-uhs-sdr25;</span><br><span style="color: hsl(120, 100%, 40%);">+ sd-uhs-ddr50;</span><br><span style="color: hsl(120, 100%, 40%);">+ sd-uhs-sdr50;</span><br><span style="color: hsl(120, 100%, 40%);">+ cap-sd-highspeed;</span><br><span style="color: hsl(120, 100%, 40%);">+ no-sdio;</span><br><span style="color: hsl(120, 100%, 40%);">+ no-mmc;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ i2c@9,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-twsi";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x4800 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-frequency = <0x186a0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0xe>;</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ idt-ptp@0x52 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "idt,82p33914-1";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x52>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ i2c@9,1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-twsi";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x4900 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clock-frequency = <0x186a0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0xe>;</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rom@54 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "atmel,24c256";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x54>;</span><br><span style="color: hsl(120, 100%, 40%);">+ pagesize = <0x40>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rtc@68 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "isil,isl12057";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x68>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tpm@0x20 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "infineon,slb9645xq-12";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x20>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rgx0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-bgx";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x9000 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ rgmii00 {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ local-mac-address = [00 00 00 00 00 00];</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bgx0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-bgx";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8000 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sgmii00 {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ qlm-mode = "0x000,sgmii";</span><br><span style="color: hsl(120, 100%, 40%);">+ local-mac-address = [00 00 00 00 00 00];</span><br><span style="color: hsl(120, 100%, 40%);">+ cavium,disable-autonegotiation;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bgx1 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-bgx";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8100 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spi@7,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8190-spi";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x3800 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0xe>;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ flash@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "micron,n25q128a13", "spi-flash";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ spi-max-frequency = <0xf42400>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio0@6,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #gpio-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8890-gpio";</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio-controller;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x3000 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ u-boot,dm-pre-reloc;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0x7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0x7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nand@b,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,cn8130-nand";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x5800 0x0 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0xe>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci@87e0c0000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,pci-host-thunder-pem";</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-parent = <0xd>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-map = <0x0 0xd 0x0 0x10000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-range = <0x1f 0x57>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #stream-id-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ dma-coherent;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8800 0x1f000000 0x0 0x39000000 0x87e0 0xc0000000 0x0 0x1000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x1000000 0x0 0x0 0x8830 0x0 0x0 0x10000 0x3000000 0x0 0x10000000 0x8810 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x8820 0x0 0x10 0x0 0x3000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x0 0x1000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #interrupt-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x10 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x11 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x13 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0xa>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0xa>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci@87e0c1000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,pci-host-thunder-pem";</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-parent = <0xd>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-map = <0x0 0xd 0x0 0x10000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-range = <0x57 0x8f>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #stream-id-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ dma-coherent;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8840 0x57000000 0x0 0x39000000 0x87e0 0xc1000000 0x0 0x1000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x1000000 0x0 0x10000 0x8870 0x10000 0x0 0x10000 0x3000000 0x0 0x10000000 0x8850 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x8860 0x0 0x10 0x0 0x3000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x0 0x1000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #interrupt-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x14 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x15 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x16 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x17 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0xb>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0xb>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci@87e0c2000000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,pci-host-thunder-pem";</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "pci";</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-parent = <0xd>;</span><br><span style="color: hsl(120, 100%, 40%);">+ msi-map = <0x0 0xd 0x0 0x10000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ bus-range = <0x8f 0xc7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x2>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x3>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #stream-id-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ dma-coherent;</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x8880 0x8f000000 0x0 0x39000000 0x87e0 0xc2000000 0x0 0x1000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ ranges = <0x1000000 0x0 0x20000 0x88b0 0x20000 0x0 0x10000 0x3000000 0x0 0x10000000 0x8890 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x88a0 0x0 0x10 0x0 0x3000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x0 0x1000000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #interrupt-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x18 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x19 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x1a 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x1b 0x4>;</span><br><span style="color: hsl(120, 100%, 40%);">+ linux,phandle = <0xc>;</span><br><span style="color: hsl(120, 100%, 40%);">+ phandle = <0xc>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tdm@d,0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ #address-cells = <0x1>;</span><br><span style="color: hsl(120, 100%, 40%);">+ #size-cells = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ compatible = "cavium,thunder-8190-tdm";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x6800 0x0 0x0 0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks = <0xe>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ aliases {</span><br><span style="color: hsl(120, 100%, 40%);">+ serial0 = "/soc@0/serial@87e028000000";</span><br><span style="color: hsl(120, 100%, 40%);">+ serial1 = "/soc@0/serial@87e029000000";</span><br><span style="color: hsl(120, 100%, 40%);">+ serial2 = "/soc@0/serial@87e02a000000";</span><br><span style="color: hsl(120, 100%, 40%);">+ serial3 = "/soc@0/serial@87e02b000000";</span><br><span style="color: hsl(120, 100%, 40%);">+ i2c0 = "/soc@0/pci@848000000000/mrml-bridge0@1,0/i2c@9,0";</span><br><span style="color: hsl(120, 100%, 40%);">+ i2c1 = "/soc@0/pci@848000000000/mrml-bridge0@1,0/i2c@9,1";</span><br><span style="color: hsl(120, 100%, 40%);">+ spi0 = "/soc@0/pci@848000000000/spi@7,0";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chosen {</span><br><span style="color: hsl(120, 100%, 40%);">+ stdout-path = "serial0:115200n8";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ memory@0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ device_type = "memory";</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = <0x0 0x1400000 0x0 0x7ec00000>;</span><br><span style="color: hsl(120, 100%, 40%);">+ numa-node-id = <0x0>;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/opencellular/elgon/mainboard.c b/src/mainboard/opencellular/elgon/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9636715</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/mainboard.c</span><br><span>@@ -0,0 +1,112 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-2018 Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2003-2017 Cavium Inc. (support@cavium.com)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-hal/bdk-config.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-hal/bdk-twsi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/uart.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/clock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/sdram.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-hal/bdk-config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_print_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: trusted boot : %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_strap_value(10) ? "yes" : "no");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t boot_method = gpio_strap_value(0) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (gpio_strap_value(1) << 1) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (gpio_strap_value(2) << 2) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (gpio_strap_value(3) << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: boot method : ");</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (boot_method) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x2:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x3:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "EMMC\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x5:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x6:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "SPI\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x8:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "REMOTE\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0xc:</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0xd:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "PCIe\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "unknown\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: REFclk : %llu MHz\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ thunderx_get_ref_clock() / 1000000ULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: IOclk : %llu MHz\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ thunderx_get_io_clock() / 1000000ULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: COREclk : %llu MHz\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ thunderx_get_core_clock() / 1000000ULL);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: #CPU cores : %zu\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_get_num_available_cores());</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "MB: RAM : %zu MiB\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_size_mb());</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern const struct bdk_devicetree_key_value devtree[];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_init(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init UARTs */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 4; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!uart_is_enabled(i))</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_setup(i, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init timer */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_timer_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init CPUs */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 1; i < CONFIG_MAX_CPUS; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ start_cpu(i, NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->ops->init = &mainboard_init;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_config_set_fdt(devtree);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_print_info();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = CONFIG_MAINBOARD_PART_NUMBER,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/opencellular/elgon/mainboard.h b/src/mainboard/opencellular/elgon/mainboard.h</span><br><span>new file mode 100644</span><br><span>index 0000000..46e6477</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/mainboard.h</span><br><span>@@ -0,0 +1,19 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define ELGON_GPIO_ERROR_LED 11</span><br><span style="color: hsl(120, 100%, 40%);">+#define ELGON_GPIO_SPI_MUX 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define ELGON_GPIO_UART_SEL 26</span><br><span>diff --git a/src/mainboard/opencellular/elgon/memlayout.ld b/src/mainboard/opencellular/elgon/memlayout.ld</span><br><span>new file mode 100644</span><br><span>index 0000000..9349362</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/memlayout.ld</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/memlayout.ld></span><br><span>diff --git a/src/mainboard/opencellular/elgon/romstage.c b/src/mainboard/opencellular/elgon/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e8e5cd6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/romstage.c</span><br><span>@@ -0,0 +1,47 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/exception.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <romstage_handoff.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/sdram.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/timer.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/mmu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <program_loading.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-hal/bdk-config.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern const struct bdk_devicetree_key_value devtree[];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void main(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ watchdog_poke(0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ exception_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_config_set_fdt(devtree);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sdram_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_mmu_init();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ watchdog_poke(0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ cbmem_initialize_empty();</span><br><span style="color: hsl(120, 100%, 40%);">+ run_ramstage();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/opencellular/elgon/vboot.fmd b/src/mainboard/opencellular/elgon/vboot.fmd</span><br><span>new file mode 100644</span><br><span>index 0000000..e6ac134</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/opencellular/elgon/vboot.fmd</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+FLASH@0x0 16M {</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0x0 0x63d4c0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_SECTION@0x0 0x6394c0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ # bootblock includes trusted/non-trusted CLIB, CSIB,</span><br><span style="color: hsl(120, 100%, 40%);">+ # and BL1FWs packaged in</span><br><span style="color: hsl(120, 100%, 40%);">+ # src/soc/cavium/common/Makefile.inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOTBLOCK@0x10000 0x70000</span><br><span style="color: hsl(120, 100%, 40%);">+ FMAP@0x80000 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT(CBFS)@0x81000 0x4c94c0</span><br><span style="color: hsl(120, 100%, 40%);">+ GBB@0x54a4c0 0xeef00</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID@0x6393c0 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_VPD@0x6394c0 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_A@0x63d4c0 0x4db5a0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_A@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_A(CBFS)@0x2000 0x4d94a0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_A@0x4db4a0 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_B@0xb18a60 0x4db5a0 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_B@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_B(CBFS)@0x2000 0x4d94a0</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_B@0x4db4a0 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_ELOG@0xff4000 0x4000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_VPD@0xff8000 0x8000</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28024">change 28024</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28024"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 </div>
<div style="display:none"> Gerrit-Change-Number: 28024 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>