<p>Philipp Deppenwiese <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/27955">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Philipp Deppenwiese: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium/cn81xx: Fix minor things<br><br>* Move cbmem.c to cn81xx folder<br>* Store CBMEM below 4 GiB<br>* Make sure CBMEM doesn't overlap with ATF scratchpad<br>* Fix ATF scratchpad not marked as reserved due to wrong calculation<br>* The scratchpad is the last 1 MiB at the end of DRAM.<br><br>Tested on Cavium CN81xx EVB:<br>The ATF scratchpad is now marked reserved and the configuration tables<br>are located below 4 GiB. Linux still boots.<br><br>Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>Reviewed-on: https://review.coreboot.org/27955<br>Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com><br>Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M src/soc/cavium/cn81xx/Makefile.inc<br>R src/soc/cavium/cn81xx/cbmem.c<br>M src/soc/cavium/cn81xx/soc.c<br>M src/soc/cavium/common/Makefile.inc<br>4 files changed, 8 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>index 845ac34..2179bc7 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>+++ b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>@@ -39,16 +39,11 @@</span><br><span> romstage-y += spi.c</span><br><span> romstage-y += uart.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-< += cpu.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += cbmem.c</span><br><span> </span><br><span> romstage-y += sdram.c</span><br><span> romstage-y += mmu.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += ../common/cbmem.c</span><br><span style="color: hsl(0, 100%, 40%);">-# BDK coreboot interface</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += ../common/bdk-coreboot.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> ################################################################################</span><br><span> # ramstage</span><br><span> </span><br><span>@@ -64,12 +59,10 @@</span><br><span> ramstage-y += cpu.c</span><br><span> ramstage-y += cpu_secondary.S</span><br><span> ramstage-y += ecam0.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += cbmem.c</span><br><span> </span><br><span> ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-# BDK coreboot interface</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += ../common/bdk-coreboot.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0</span><br><span> </span><br><span> CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include</span><br><span>diff --git a/src/soc/cavium/common/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c</span><br><span>similarity index 82%</span><br><span>rename from src/soc/cavium/common/cbmem.c</span><br><span>rename to src/soc/cavium/cn81xx/cbmem.c</span><br><span>index 401f8b2..397fd26 100644</span><br><span>--- a/src/soc/cavium/common/cbmem.c</span><br><span>+++ b/src/soc/cavium/cn81xx/cbmem.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> </span><br><span> void *cbmem_top(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,</span><br><span style="color: hsl(0, 100%, 40%);">- MAX_DRAM_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Make sure not to overlap with reserved ATF scratchpad */</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ 4ULL * GiB);</span><br><span> }</span><br><span>diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c</span><br><span>index b575ca4..8efcb13 100644</span><br><span>--- a/src/soc/cavium/cn81xx/soc.c</span><br><span>+++ b/src/soc/cavium/cn81xx/soc.c</span><br><span>@@ -309,7 +309,8 @@</span><br><span> BM_MEM_RESERVED);</span><br><span> </span><br><span> /* Scratchpad for ATF SATA quirks */</span><br><span style="color: hsl(0, 100%, 40%);">- bootmem_add_range(sdram_size_mb() * KiB, 1 * MiB, BM_MEM_RESERVED);</span><br><span style="color: hsl(120, 100%, 40%);">+ bootmem_add_range((sdram_size_mb() - 1) * MiB, 1 * MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ BM_MEM_RESERVED);</span><br><span> }</span><br><span> </span><br><span> static void soc_read_resources(device_t dev)</span><br><span>diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc</span><br><span>index 7af8bf5..ada8286 100644</span><br><span>--- a/src/soc/cavium/common/Makefile.inc</span><br><span>+++ b/src/soc/cavium/common/Makefile.inc</span><br><span>@@ -22,13 +22,12 @@</span><br><span> ################################################################################</span><br><span> # romstage</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += cbmem.c</span><br><span> romstage-y += bdk-coreboot.c</span><br><span> </span><br><span> ################################################################################</span><br><span> # ramstage</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += cbmem.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += bdk-coreboot.c</span><br><span> </span><br><span> CPPFLAGS_common += -Isrc/soc/cavium/common/include</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27955">change 27955</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74 </div>
<div style="display:none"> Gerrit-Change-Number: 27955 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
<div style="display:none"> Gerrit-Reviewer: David Hendricks <david.hendricks@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>