<p>Michał Żygowski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27989">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">minnowmax: allow both 1333 and 1066 MHz memory SKUs<br><br>The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds.<br>Use frequency as a proxy to determine SKU. The E3805, E3815,<br>E3825, and E3826 are all <= 1460MHz while the E3827 and E3845<br>are 1750MHz and 1910MHz, respectively. This will allow to boot<br>quad-core Minnowboard Turbot especially.<br><br>Change-Id: I5e57dd419b443dfa742c8812cec87274af557728<br>Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com><br>---<br>M src/mainboard/intel/minnowmax/romstage.c<br>1 file changed, 58 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27989/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c</span><br><span>index 6f40207..b962c55 100644</span><br><span>--- a/src/mainboard/intel/minnowmax/romstage.c</span><br><span>+++ b/src/mainboard/intel/minnowmax/romstage.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <soc/intel/fsp_baytrail/chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/tsc.h></span><br><span> </span><br><span> /**</span><br><span> * /brief mainboard call for setup that needs to be done before fsp init</span><br><span>@@ -50,11 +51,68 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Set up the default soldered down memory config for 1GB */</span><br><span style="color: hsl(120, 100%, 40%);">+static const MEMORY_DOWN_DATA minnowmax_memory_config[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1066 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .EnableMemoryDown = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .DRAMSpeed = 1, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMM0Enable = 1, /* DIMM 0 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMM1Enable = 0, /* DIMM 1 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtCL = 11, /* tCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRPtRCD = 11, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtWR = 12, /* tWR in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtWTR = 6, /* tWTR in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRRD = 6, /* tRRD in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRTP = 6, /* tRTP in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtFAW = 20, /* tFAW in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1333 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .EnableMemoryDown = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .DRAMSpeed = 2, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMM0Enable = 1, /* DIMM 0 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMM1Enable = 0, /* DIMM 1 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtCL = 9, /* tCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRPtRCD = 9, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtWR = 10, /* tWR in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtWTR = 5, /* tWTR in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRRD = 4, /* tRRD in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRTP = 5, /* tRTP in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtFAW = 30, /* tFAW in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)</span><br><span> {</span><br><span> UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;</span><br><span> u8 use_xhci = UpdData->PcdEnableXhci;</span><br><span> u8 gpio5 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ int is_1333_sku;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. There's</span><br><span style="color: hsl(120, 100%, 40%);">+ * no good way of knowing the SKU'ing so frequency is used as a proxy.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the</span><br><span style="color: hsl(120, 100%, 40%);">+ * E3827 and E3845 are 1750MHz and 1910MHz, respectively.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ is_1333_sku = !!(tsc_freq_mhz() >= 1700);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Using %d MHz DDR3 settings.\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ is_1333_sku ? 1333 : 1066);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set up soldered down memory parameters for 1GB */</span><br><span style="color: hsl(120, 100%, 40%);">+ UpdData->PcdMemoryParameters = minnowmax_memory_config[is_1333_sku];</span><br><span> </span><br><span> /*</span><br><span> * Minnow Max Board</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27989">change 27989</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5e57dd419b443dfa742c8812cec87274af557728 </div>
<div style="display:none"> Gerrit-Change-Number: 27989 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>