<p><a href="https://review.coreboot.org/27972">View Change</a></p><p>5 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c">File src/arch/riscv/misaligend.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@176">Patch Set #3, Line 176:</a> <code style="font-family:monospace,monospace">              int regnum = ((insn >> match->reg_shift) & match->reg_mask) + match->reg_addition;</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@184">Patch Set #3, Line 184:</a> <code style="font-family:monospace,monospace">                          buff.b[i] = mprv_read_u8((uint8_t *)(tf->badvaddr + i));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@237">Patch Set #3, Line 237:</a> <code style="font-family:monospace,monospace">                    /* writing to memory by bytes prevents misaligned memory access */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@239">Patch Set #3, Line 239:</a> <code style="font-family:monospace,monospace">                             mprv_write_u8((uint8_t *)(tf->badvaddr + i), buff.b[i]);</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27972/3/src/arch/riscv/trap_handler.c">File src/arch/riscv/trap_handler.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27972/3/src/arch/riscv/trap_handler.c@191">Patch Set #3, Line 191:</a> <code style="font-family:monospace,monospace">       write_csr(sepc, read_csr(mepc));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">'sepc' may be misspelled - perhaps 'spec'?</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/27972">change 27972</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27972"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: comment </div>
<div style="display:none"> Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f </div>
<div style="display:none"> Gerrit-Change-Number: 27972 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-Comment-Date: Thu, 09 Aug 2018 08:24:48 +0000 </div>
<div style="display:none"> Gerrit-HasComments: Yes </div>
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