<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27988">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Fix typo<br><br>Change-Id: I689c5663ef59861f79b68220abd146144f7618de<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/lib/rmodule.ld<br>M src/northbridge/amd/amdfam10/misc_control.c<br>M src/northbridge/amd/amdmct/mct/mctecc_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c<br>M src/northbridge/amd/amdmct/wrappers/mcti_d.c<br>M src/northbridge/amd/lx/northbridgeinit.c<br>M src/northbridge/intel/gm45/raminit.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/intel/x4x/raminit_tables.c<br>M src/northbridge/via/vx900/raminit_ddr3.c<br>M src/security/tpm/tss/tcg-2.0/tss_marshaling.c<br>M src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h<br>M src/soc/intel/cannonlake/reset.c<br>M src/soc/intel/common/block/cse/cse.c<br>M src/soc/intel/skylake/bootblock/pch.c<br>M src/soc/intel/skylake/include/soc/iomap.h<br>M src/soc/rockchip/common/include/soc/spi.h<br>M src/soc/samsung/exynos5420/include/soc/memlayout.ld<br>M src/soc/samsung/exynos5420/include/soc/setup.h<br>20 files changed, 27 insertions(+), 27 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/27988/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld</span><br><span>index 340fe7a..ddf7925 100644</span><br><span>--- a/src/lib/rmodule.ld</span><br><span>+++ b/src/lib/rmodule.ld</span><br><span>@@ -6,7 +6,7 @@</span><br><span> * NOTE: The program's loadable sections (text, module_params, and data) are</span><br><span> * packed into the flat blob. The rmodule loader assumes the entire program</span><br><span> * resides in one contiguous address space. Therefore, alignment for a given</span><br><span style="color: hsl(0, 100%, 40%);">- * section (if required) needs to be done at the end of the preceeding section.</span><br><span style="color: hsl(120, 100%, 40%);">+ * section (if required) needs to be done at the end of the preceding section.</span><br><span> * e.g. if the data section should be aligned to an 8 byte address the text</span><br><span> * section should have ALIGN(8) at the end of its section. Otherwise there</span><br><span> * won't be a consistent mapping between the flat blob and the loaded program.</span><br><span>diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c</span><br><span>index 028f6af..8323c1e 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/misc_control.c</span><br><span>+++ b/src/northbridge/amd/amdfam10/misc_control.c</span><br><span>@@ -19,7 +19,7 @@</span><br><span> </span><br><span> /* Turn off machine check triggers when reading</span><br><span> * pci space where there are no devices.</span><br><span style="color: hsl(0, 100%, 40%);">- * This is necessary when scaning the bus for</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is necessary when scanning the bus for</span><br><span> * devices which is done by the kernel</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c</span><br><span>index 18774eb..7be6353 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c</span><br><span>@@ -68,7 +68,7 @@</span><br><span> * (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the</span><br><span> * scrubber is used in two steps. First, the Dram Limit for the node is adjusted</span><br><span> * down to the bottom of the gap, and that ECC dram is initialized. Second, the</span><br><span style="color: hsl(0, 100%, 40%);">- * orignal Limit is restored, the Scrub base is set to 4GB, and scrubber is</span><br><span style="color: hsl(120, 100%, 40%);">+ * original Limit is restored, the Scrub base is set to 4GB, and scrubber is</span><br><span> * allowed to run until the Scrub Addr wraps around to zero.</span><br><span> */</span><br><span> u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c</span><br><span>index 31c23b9..20a636e 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c</span><br><span>@@ -83,7 +83,7 @@</span><br><span> * (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the</span><br><span> * scrubber is used in two steps. First, the Dram Limit for the node is adjusted</span><br><span> * down to the bottom of the gap, and that ECC dram is initialized. Second, the</span><br><span style="color: hsl(0, 100%, 40%);">- * orignal Limit is restored, the Scrub base is set to 4GB, and scrubber is</span><br><span style="color: hsl(120, 100%, 40%);">+ * original Limit is restored, the Scrub base is set to 4GB, and scrubber is</span><br><span> * allowed to run until the Scrub Addr wraps around to zero.</span><br><span> */</span><br><span> u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c</span><br><span>index ed942ea..f62aa15 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c</span><br><span>@@ -924,7 +924,7 @@</span><br><span> u8 WrLvOdt1 = 0;</span><br><span> </span><br><span> if (is_fam15h()) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* On Family15h processors, the value for the specific CS being targetted</span><br><span style="color: hsl(120, 100%, 40%);">+ /* On Family15h processors, the value for the specific CS being targeted</span><br><span> * is taken from F2x238 / F2x23C as appropriate, then loaded into F2x9C_x0000_0008</span><br><span> */</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c</span><br><span>index 3d9ff3e..bcf3ddc 100644</span><br><span>--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c</span><br><span>@@ -170,7 +170,7 @@</span><br><span> case NV_SPDCHK_RESTRT:</span><br><span> val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */</span><br><span> //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */</span><br><span style="color: hsl(0, 100%, 40%);">- //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */</span><br><span style="color: hsl(120, 100%, 40%);">+ //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node initialization */</span><br><span> </span><br><span> if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS)</span><br><span> val = nvram & 0x3;</span><br><span>diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c</span><br><span>index 6c2efb3..c7db156 100644</span><br><span>--- a/src/northbridge/amd/lx/northbridgeinit.c</span><br><span>+++ b/src/northbridge/amd/lx/northbridgeinit.c</span><br><span>@@ -122,7 +122,7 @@</span><br><span> int sizembytes, sizebytes;</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Figure out how much RAM is in the machine and alocate all to the</span><br><span style="color: hsl(120, 100%, 40%);">+ * Figure out how much RAM is in the machine and allocate all to the</span><br><span> * system. We will adjust for SMM now and Frame Buffer later.</span><br><span> */</span><br><span> sizembytes = sizeram();</span><br><span>@@ -272,7 +272,7 @@</span><br><span> * base of 1M and top of around 256M</span><br><span> */</span><br><span> /* we have to create a page-aligned (4KB page) address for base and top */</span><br><span style="color: hsl(0, 100%, 40%);">- /* So we need a high page aligned addresss (pah) and low page aligned address (pal)</span><br><span style="color: hsl(120, 100%, 40%);">+ /* So we need a high page aligned address (pah) and low page aligned address (pal)</span><br><span> * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12</span><br><span> */</span><br><span> pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);</span><br><span>diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c</span><br><span>index 08f954d..03f617c 100644</span><br><span>--- a/src/northbridge/intel/gm45/raminit.c</span><br><span>+++ b/src/northbridge/intel/gm45/raminit.c</span><br><span>@@ -869,7 +869,7 @@</span><br><span> </span><br><span> static void rcomp_initialization(const stepping_t stepping, const int sff)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Programm RCOMP codes. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program RCOMP codes. */</span><br><span> if (sff)</span><br><span> die("SFF platform unsupported in RCOMP initialization.\n");</span><br><span> /* Values are for DDR3. */</span><br><span>@@ -1825,7 +1825,7 @@</span><br><span> /* Some last optimizations. */</span><br><span> dram_optimizations(timings, dimms);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Mark raminit beeing finished. :-) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Mark raminit being finished. :-) */</span><br><span> u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7);</span><br><span> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8);</span><br><span> </span><br><span>diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c</span><br><span>index 66f0a10..2a1e34c 100644</span><br><span>--- a/src/northbridge/intel/pineview/raminit.c</span><br><span>+++ b/src/northbridge/intel/pineview/raminit.c</span><br><span>@@ -1972,7 +1972,7 @@</span><br><span> MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000)</span><br><span> | (curcoarse << 16);</span><br><span> if (curcoarse == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- PRINTK_DEBUG("Error: DQS didnt hit 0\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ PRINTK_DEBUG("Error: DQS did not hit 0\n");</span><br><span> break;</span><br><span> }</span><br><span> }</span><br><span>diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c</span><br><span>index 401af15..ebd1562 100644</span><br><span>--- a/src/northbridge/intel/x4x/raminit_tables.c</span><br><span>+++ b/src/northbridge/intel/x4x/raminit_tables.c</span><br><span>@@ -332,7 +332,7 @@</span><br><span> {0x0189, 0x000aaa}, /* CAS = 5 */</span><br><span> {0x0189, 0x101aaa}, /* CAS = 6 */</span><br><span> {0x0000, 0x000000}, /* CAS = 7 - Not supported */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x0000, 0x000000} /* CAS = 8 - Not suppported */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x0000, 0x000000} /* CAS = 8 - Not supported */</span><br><span> },</span><br><span> { /* DDR3 1067 */</span><br><span> {0x0000, 0x000000}, /* CAS = 5 - Not supported */</span><br><span>diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>index eec4aa3..17a87bb 100644</span><br><span>--- a/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>+++ b/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span> *</span><br><span> * The capture window is not calibrated, but preset. Whether that preset is</span><br><span> * universal or frequency dependent, and whether it is board-specific or not is</span><br><span style="color: hsl(0, 100%, 40%);">- * not yet clear. @see vx900_dram_calibrate_recieve_delays().</span><br><span style="color: hsl(120, 100%, 40%);">+ * not yet clear. @see vx900_dram_calibrate_receive_delays().</span><br><span> *</span><br><span> * 4GBit and 8GBit modules may not work. This is untested. Modules with 11</span><br><span> * column address bits are not tested. @see vx900_dram_map_row_col_bank()</span><br><span>@@ -166,7 +166,7 @@</span><br><span> {0x66, 0x80}, /* DRAM Queue / Arbitration */</span><br><span> {0x69, 0xc6}, /* Bank Control: 8 banks, high priority refresh */</span><br><span> {0x6a, 0xfc}, /* DRAMC Request Reorder Control */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x6e, 0x38}, /* Burst lenght: 8, burst-chop: enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x6e, 0x38}, /* Burst length: 8, burst-chop: enable */</span><br><span> {0x73, 0x04}, /* Close All Pages Threshold */</span><br><span> </span><br><span> /* The following need to be dynamically asserted */</span><br><span>@@ -1224,7 +1224,7 @@</span><br><span> vx900_write_0x78_0x7f(dly->avg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void vx900_dram_calibrate_recieve_delays(vx900_delay_calib * delays,</span><br><span style="color: hsl(120, 100%, 40%);">+static void vx900_dram_calibrate_receive_delays(vx900_delay_calib * delays,</span><br><span> u8 pinswap)</span><br><span> {</span><br><span> size_t n_tries = 0;</span><br><span>@@ -1417,7 +1417,7 @@</span><br><span> /* Only run on first rank, remember? */</span><br><span> break;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- vx900_dram_calibrate_recieve_delays(&delay_cal,</span><br><span style="color: hsl(120, 100%, 40%);">+ vx900_dram_calibrate_receive_delays(&delay_cal,</span><br><span> ranks->flags[i].pins_mirrored);</span><br><span> printram("RX DQS calibration results\n");</span><br><span> dump_delay_range(delay_cal.rx_dqs);</span><br><span>diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c</span><br><span>index 94bfbcf..ad23d9b 100644</span><br><span>--- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c</span><br><span>+++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c</span><br><span>@@ -222,7 +222,7 @@</span><br><span> return rc;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* TPM2_Clear command does not require paramaters. */</span><br><span style="color: hsl(120, 100%, 40%);">+/* TPM2_Clear command does not require parameters. */</span><br><span> static int marshal_clear(struct obuf *ob)</span><br><span> {</span><br><span> const uint32_t handle[] = { TPM_RH_PLATFORM };</span><br><span>diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h</span><br><span>index 93489bb..7e233fa 100644</span><br><span>--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h</span><br><span>+++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h</span><br><span>@@ -38,7 +38,7 @@</span><br><span> #endif /* GET & SET */</span><br><span> </span><br><span> /***************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Comand control registers</span><br><span style="color: hsl(120, 100%, 40%);">+ *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Command control registers</span><br><span> ***************************************************************************/</span><br><span> #define DDR34_CORE_PHY_CONTROL_REGS_REVISION 0x00000000 /* Address & Control revision register */</span><br><span> #define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS 0x00000004 /* PHY PLL status register */</span><br><span>diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c</span><br><span>index 26f0a63..140fbff 100644</span><br><span>--- a/src/soc/intel/cannonlake/reset.c</span><br><span>+++ b/src/soc/intel/cannonlake/reset.c</span><br><span>@@ -74,7 +74,7 @@</span><br><span> printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n");</span><br><span> return -1;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Heci recieve success!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Heci receive success!\n");</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c</span><br><span>index 8651297..4b53117 100644</span><br><span>--- a/src/soc/intel/common/block/cse/cse.c</span><br><span>+++ b/src/soc/intel/common/block/cse/cse.c</span><br><span>@@ -443,7 +443,7 @@</span><br><span> do {</span><br><span> received = recv_one_message(&hdr, p, left);</span><br><span> if (!received) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "HECI: Failed to recieve!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "HECI: Failed to receive!\n");</span><br><span> return 0;</span><br><span> }</span><br><span> left -= received;</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>index 4c88ed5..26ea56a 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>@@ -124,7 +124,7 @@</span><br><span> pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);</span><br><span> </span><br><span> /* Program TCO Base */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDRESS);</span><br><span> </span><br><span> /* Enable TCO in SMBUS */</span><br><span> pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);</span><br><span>@@ -133,7 +133,7 @@</span><br><span> * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]</span><br><span> * to [SMBUS PCI offset 50h[15:5], 1].</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDRESS | (1 << 1));</span><br><span> </span><br><span> /* Program TCO timer halt */</span><br><span> tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h</span><br><span>index f2fde71..475d79d 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/iomap.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/iomap.h</span><br><span>@@ -87,7 +87,7 @@</span><br><span> #define ACPI_BASE_ADDRESS 0x1800</span><br><span> #define ACPI_BASE_SIZE 0x100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define TCO_BASE_ADDDRESS 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_ADDRESS 0x400</span><br><span> #define TCO_BASE_SIZE 0x20</span><br><span> </span><br><span> #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS</span><br><span>diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h</span><br><span>index 0e1847c..ce5de83 100644</span><br><span>--- a/src/soc/rockchip/common/include/soc/spi.h</span><br><span>+++ b/src/soc/rockchip/common/include/soc/spi.h</span><br><span>@@ -101,9 +101,9 @@</span><br><span> /* SSN to Sclk_out delay */</span><br><span> #define SPI_SSN_DELAY_OFFSET 10</span><br><span> #define SPI_SSN_DELAY_MASK 0x1</span><br><span style="color: hsl(0, 100%, 40%);">-/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */</span><br><span style="color: hsl(120, 100%, 40%);">+/* the period between ss_n active and sclk_out active is half sclk_out cycles */</span><br><span> #define SPI_SSN_DELAY_HALF 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */</span><br><span style="color: hsl(120, 100%, 40%);">+/* the period between ss_n active and sclk_out active is one sclk_out cycle */</span><br><span> #define SPI_SSN_DELAY_ONE 0x01</span><br><span> </span><br><span> /* Serial Endian Mode */</span><br><span>diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld</span><br><span>index 1f13bb9..bc5d066 100644</span><br><span>--- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld</span><br><span>@@ -26,7 +26,7 @@</span><br><span> {</span><br><span> SRAM_START(0x2020000)</span><br><span> /* 17K hole, includes BL1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bootblock is preceeded by 16 byte variable length BL2 checksum. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bootblock is preceded by 16 byte variable length BL2 checksum. */</span><br><span> BOOTBLOCK(0x2024410, 32K - 16)</span><br><span> /* 15K hole */</span><br><span> ROMSTAGE(0x2030000, 128K)</span><br><span>diff --git a/src/soc/samsung/exynos5420/include/soc/setup.h b/src/soc/samsung/exynos5420/include/soc/setup.h</span><br><span>index f024a2d..139f5b7 100644</span><br><span>--- a/src/soc/samsung/exynos5420/include/soc/setup.h</span><br><span>+++ b/src/soc/samsung/exynos5420/include/soc/setup.h</span><br><span>@@ -729,7 +729,7 @@</span><br><span> #define CTRL_RDLAT_OFFSET 0</span><br><span> </span><br><span> #define CMD_DEFAULT_LPDDR3 0xF</span><br><span style="color: hsl(0, 100%, 40%);">-#define CMD_DEFUALT_OFFSET 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CMD_DEFAULT_OFFSET 0</span><br><span> #define T_WRDATA_EN 0x7</span><br><span> #define T_WRDATA_EN_DDR3 0x8 /* FIXME(dhendrix): 6 for DDR3? see T_wrdata_en */</span><br><span> #define T_WRDATA_EN_OFFSET 16</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27988">change 27988</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I689c5663ef59861f79b68220abd146144f7618de </div>
<div style="display:none"> Gerrit-Change-Number: 27988 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>