<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27968">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus: Use correct chip for CNVi device<br><br>This change uses drivers/intel/wifi chip for CNVi device to ensure<br>that:<br>1. Correct device name shows up in ACPI node<br>2. It is possible to pass any parameters from devicetree to wifi<br>driver for SSDT generation.<br><br>BUG=b:112371978<br><br>Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/mainboard/google/octopus/variants/baseboard/devicetree.cb<br>1 file changed, 3 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27968/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>index b7c7ad2..1a6dac9 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>@@ -112,7 +112,9 @@</span><br><span>               device pci 00.2 off end # - NPK</span><br><span>              device pci 02.0 on  end # - Gen</span><br><span>              device pci 03.0 on  end # - Iunit</span><br><span style="color: hsl(0, 100%, 40%);">-               device pci 0c.0 on  end # - CNVi</span><br><span style="color: hsl(120, 100%, 40%);">+              chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+                       device pci 0c.0 on  end # - CNVi</span><br><span style="color: hsl(120, 100%, 40%);">+              end</span><br><span>          device pci 0d.0 on  end # - P2SB</span><br><span>             device pci 0d.1 on  end # - PMC</span><br><span>              device pci 0d.2 on  end # - Fast SPI</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27968">change 27968</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27968"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0 </div>
<div style="display:none"> Gerrit-Change-Number: 27968 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>