<p>Tristan Hsieh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27974">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mediatek: Map SRAM as secure and cached memory<br><br>This patch changes the mapping of SRAM from non-secure to secure.<br>Without this patch, mmu_config_range() can not work when MMU is<br>enabled. The new config is still in non-secure cache since TTB section<br>is allocated in SRAM which is mapped as non-secure.<br><br>BUG=b:80501386<br>TEST=Boots correctly on Kukui<br><br>Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6<br>Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com><br>---<br>M src/soc/mediatek/common/include/soc/mmu_operations.h<br>M src/soc/mediatek/common/mmu_operations.c<br>2 files changed, 11 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27974/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h</span><br><span>index b081690..79c3ea0 100644</span><br><span>--- a/src/soc/mediatek/common/include/soc/mmu_operations.h</span><br><span>+++ b/src/soc/mediatek/common/include/soc/mmu_operations.h</span><br><span>@@ -19,10 +19,11 @@</span><br><span> #include <arch/mmu.h></span><br><span> </span><br><span> enum {</span><br><span style="color: hsl(0, 100%, 40%);">-   DEV_MEM         = MA_DEV | MA_S  | MA_RW,</span><br><span style="color: hsl(0, 100%, 40%);">-       CACHED_MEM      = MA_MEM | MA_NS | MA_RW,</span><br><span style="color: hsl(0, 100%, 40%);">-       SECURE_MEM      = MA_MEM | MA_S  | MA_RW,</span><br><span style="color: hsl(0, 100%, 40%);">-       UNCACHED_MEM    = MA_MEM | MA_NS | MA_RW | MA_MEM_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEV_MEM                 = MA_DEV | MA_S  | MA_RW,</span><br><span style="color: hsl(120, 100%, 40%);">+     SECURE_CACHED_MEM       = MA_MEM | MA_S  | MA_RW,</span><br><span style="color: hsl(120, 100%, 40%);">+     SECURE_UNCACHED_MEM     = MA_MEM | MA_S  | MA_RW | MA_MEM_NC,</span><br><span style="color: hsl(120, 100%, 40%);">+ NONSECURE_CACHED_MEM    = MA_MEM | MA_NS | MA_RW,</span><br><span style="color: hsl(120, 100%, 40%);">+     NONSECURE_UNCACHED_MEM  = MA_MEM | MA_NS | MA_RW | MA_MEM_NC,</span><br><span> };</span><br><span> </span><br><span> extern unsigned char _sram_l2c[];</span><br><span>diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c</span><br><span>index b991084..78a1a44 100644</span><br><span>--- a/src/soc/mediatek/common/mmu_operations.c</span><br><span>+++ b/src/soc/mediatek/common/mmu_operations.c</span><br><span>@@ -26,16 +26,17 @@</span><br><span>      mmu_init();</span><br><span> </span><br><span>      /* Set 0x0 to the end of 2GB dram address as device memory */</span><br><span style="color: hsl(0, 100%, 40%);">-   mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+    mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM);</span><br><span> </span><br><span>       /* SRAM is cached */</span><br><span style="color: hsl(0, 100%, 40%);">-    mmu_config_range(_sram, _sram_size, CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+      mmu_config_range(_sram, _sram_size, SECURE_CACHED_MEM);</span><br><span> </span><br><span>  /* L2C SRAM is cached */</span><br><span style="color: hsl(0, 100%, 40%);">-        mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+      mmu_config_range(_sram_l2c, _sram_l2c_size, SECURE_CACHED_MEM);</span><br><span> </span><br><span>  /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */</span><br><span style="color: hsl(0, 100%, 40%);">-    mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+    mmu_config_range(_dma_coherent, _dma_coherent_size,</span><br><span style="color: hsl(120, 100%, 40%);">+                    SECURE_UNCACHED_MEM);</span><br><span> </span><br><span>   mmu_enable();</span><br><span> }</span><br><span>@@ -43,7 +44,7 @@</span><br><span> void mtk_mmu_after_dram(void)</span><br><span> {</span><br><span>         /* Map DRAM as cached now that it's up and running */</span><br><span style="color: hsl(0, 100%, 40%);">-       mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);</span><br><span style="color: hsl(120, 100%, 40%);">+ mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM);</span><br><span> </span><br><span>  mtk_soc_after_dram();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27974">change 27974</a>. To unsubscribe, or for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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6 </div>
<div style="display:none"> Gerrit-Change-Number: 27974 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Hsieh <tristan.shieh@mediatek.com> </div>