<p>Xiang Wang <strong>uploaded patch set #5</strong> to this change.</p><p><a href="https://review.coreboot.org/27972">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">riscv: update misaligned memory access exception handling<br><br>Support for more situations: floating point, compressed instructions,<br>etc. Add support for redirect exception to S-Mode. fix DEFINE_MPRV_READ<br>to support that reading the page which is executable-only (R=0 X=1).<br><br>Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f<br>Signed-off-by: Xiang Wang <wxjstz@126.com><br>---<br>M src/arch/riscv/Makefile.inc<br>A src/arch/riscv/fp_asm.S<br>M src/arch/riscv/include/arch/exception.h<br>M src/arch/riscv/include/vm.h<br>A src/arch/riscv/misaligend.c<br>M src/arch/riscv/trap_handler.c<br>6 files changed, 619 insertions(+), 65 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27972/5</pre><p>To view, visit <a href="https://review.coreboot.org/27972">change 27972</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27972"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f </div>
<div style="display:none"> Gerrit-Change-Number: 27972 </div>
<div style="display:none"> Gerrit-PatchSet: 5 </div>
<div style="display:none"> Gerrit-Owner: Xiang Wang <wxjstz@126.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>