<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27922">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/amd: Rename MCA status register<br><br>Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its<br>MC0_STATUS address.<br><br>Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/cpu/amd/agesa/family12/model_12_init.c<br>M src/cpu/amd/agesa/family14/model_14_init.c<br>M src/cpu/amd/agesa/family15tn/model_15_init.c<br>M src/cpu/amd/agesa/family16kb/model_16_init.c<br>M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>M src/cpu/amd/pi/00630F01/model_15_init.c<br>M src/cpu/amd/pi/00660F01/model_15_init.c<br>M src/cpu/amd/pi/00730F01/model_16_init.c<br>M src/include/cpu/amd/amdfam15.h<br>M src/include/cpu/amd/amdfam16.h<br>M src/soc/amd/stoneyridge/cpu.c<br>11 files changed, 14 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/27922/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c</span><br><span>index b4757c8..afdfb3b 100644</span><br><span>--- a/src/cpu/amd/agesa/family12/model_12_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family12/model_12_init.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> #include <cpu/amd/multicore.h></span><br><span> #include <cpu/amd/amdfam12.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MCI_STATUS 0x401</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC0_STATUS 0x401</span><br><span> </span><br><span> static void model_12_init(struct device *dev)</span><br><span> {</span><br><span>@@ -55,7 +55,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0; i < 5; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span> enable_cache();</span><br><span>diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>index 1271a4e..257f81f 100644</span><br><span>--- a/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>@@ -28,7 +28,7 @@</span><br><span> #include <arch/acpi.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MCI_STATUS 0x401</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC0_STATUS 0x401</span><br><span> </span><br><span> static void model_14_init(struct device *dev)</span><br><span> {</span><br><span>@@ -78,7 +78,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0; i < 6; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span> /* Enable the local CPU APICs */</span><br><span>diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>index 32dcd7b..1e0375f 100644</span><br><span>--- a/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>@@ -75,7 +75,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0; i < 6; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span> /* Enable the local CPU APICs */</span><br><span>diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>index 73d91e7..9909793 100644</span><br><span>--- a/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>@@ -73,7 +73,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0; i < 6; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span> /* Enable the local CPU APICs */</span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>index 562a267..61eb813 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>@@ -32,7 +32,7 @@</span><br><span> #include <cpu/amd/multicore.h></span><br><span> #include <cpu/amd/msr.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MCI_STATUS 0x401</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC0_STATUS 0x401</span><br><span> </span><br><span> static inline uint8_t is_gt_rev_d(void)</span><br><span> {</span><br><span>@@ -112,7 +112,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0; i < 5; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span> enable_cache();</span><br><span>diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>index 212d705..592ca4f 100644</span><br><span>--- a/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>+++ b/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>@@ -72,7 +72,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0; i < 6; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> </span><br><span> /* Enable the local CPU APICs */</span><br><span> setup_lapic();</span><br><span>diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>index 941c48f..24c2aea 100644</span><br><span>--- a/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>+++ b/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>@@ -84,7 +84,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0; i < 6; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> </span><br><span> </span><br><span> /* Enable the local CPU APICs */</span><br><span>diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>index 747cb2e..b9e0185 100644</span><br><span>--- a/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>+++ b/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>@@ -69,7 +69,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0; i < 6; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> </span><br><span> </span><br><span> /* Enable the local CPU APICs */</span><br><span>diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h</span><br><span>index 008d5da..c28ec13 100644</span><br><span>--- a/src/include/cpu/amd/amdfam15.h</span><br><span>+++ b/src/include/cpu/amd/amdfam15.h</span><br><span>@@ -16,7 +16,7 @@</span><br><span> #ifndef CPU_AMD_FAM15_H</span><br><span> #define CPU_AMD_FAM15_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MCI_STATUS 0x00000401</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC0_STATUS 0x00000401</span><br><span> #define MSR_SMM_BASE 0xC0010111</span><br><span> #define MSR_TSEG_BASE 0xC0010112</span><br><span> #define MSR_SMM_MASK 0xC0010113</span><br><span>diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h</span><br><span>index 861e518..8d8be83 100644</span><br><span>--- a/src/include/cpu/amd/amdfam16.h</span><br><span>+++ b/src/include/cpu/amd/amdfam16.h</span><br><span>@@ -16,7 +16,7 @@</span><br><span> #ifndef CPU_AMD_FAM16_H</span><br><span> #define CPU_AMD_FAM16_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define MCI_STATUS 0x00000401</span><br><span style="color: hsl(120, 100%, 40%);">+#define MC0_STATUS 0x00000401</span><br><span> #define HWCR_MSR 0xC0010015</span><br><span> #define NB_CFG_MSR 0xC001001f</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c</span><br><span>index 4dd371c..6289174 100644</span><br><span>--- a/src/soc/amd/stoneyridge/cpu.c</span><br><span>+++ b/src/soc/amd/stoneyridge/cpu.c</span><br><span>@@ -126,7 +126,7 @@</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span> for (i = 0 ; i < 6 ; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MCI_STATUS + (i * 4), msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> </span><br><span> setup_lapic();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27922">change 27922</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27922"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 </div>
<div style="display:none"> Gerrit-Change-Number: 27922 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>