<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27911">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/northbridge: Fix typo<br><br>Change-Id: I00094028036f33892362b935899e1bceef1da625<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/amd/amdfam10/amdfam10.h<br>M src/northbridge/amd/amdfam10/resourcemap.c<br>M src/northbridge/amd/amdht/h3ffeat.h<br>M src/northbridge/amd/amdht/h3ncmn.c<br>M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c<br>M src/northbridge/amd/amdmct/wrappers/mcti_d.c<br>M src/northbridge/intel/gm45/ram_calc.c<br>M src/northbridge/intel/i945/ram_calc.c<br>M src/northbridge/intel/pineview/ram_calc.c<br>M src/northbridge/intel/x4x/ram_calc.c<br>10 files changed, 14 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/27911/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h</span><br><span>index b744e96..5102b0b 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/amdfam10.h</span><br><span>+++ b/src/northbridge/amd/amdfam10/amdfam10.h</span><br><span>@@ -314,7 +314,7 @@</span><br><span> </span><br><span> // for 0x98 index and 0x9c data for DCT0</span><br><span> // for 0x198 index and 0x19c data for DCT1</span><br><span style="color: hsl(0, 100%, 40%);">-// even at ganged mode, 0x198/0x19c will be used for channnel B</span><br><span style="color: hsl(120, 100%, 40%);">+// even at ganged mode, 0x198/0x19c will be used for channel B</span><br><span> </span><br><span> #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98</span><br><span> #define DCAO_DctOffset_SHIFT 0</span><br><span>@@ -368,9 +368,9 @@</span><br><span> #define DODCC_ProcOdt_75_OHMS 2</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs</span><br><span style="color: hsl(0, 100%, 40%);">- for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0</span><br><span style="color: hsl(0, 100%, 40%);">- F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1</span><br><span style="color: hsl(120, 100%, 40%);">+ for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs</span><br><span style="color: hsl(120, 100%, 40%);">+ for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0</span><br><span style="color: hsl(120, 100%, 40%);">+ F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1</span><br><span> So Socket F with Four Logical DIMM will only support DDR2 800 ?</span><br><span> */</span><br><span> /* there are index +100 ===> for DIMM1</span><br><span>diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c</span><br><span>index 5db6886..362872b 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/resourcemap.c</span><br><span>+++ b/src/northbridge/amd/amdfam10/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit</span><br><span> * address that defines the end of a memory-mapped</span><br><span> * I/O region n</span><br><span> */</span><br><span>diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h</span><br><span>index 59e8feb..2cf4bd1 100644</span><br><span>--- a/src/northbridge/amd/amdht/h3ffeat.h</span><br><span>+++ b/src/northbridge/amd/amdht/h3ffeat.h</span><br><span>@@ -157,7 +157,7 @@</span><br><span> */</span><br><span> sPortDescriptor PortList[MAX_PLATFORM_LINKS*2];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */</span><br><span> u8 sysDegree[MAX_NODES];</span><br><span> /* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */</span><br><span> BOOL sysMatrix[MAX_NODES][MAX_NODES];</span><br><span>@@ -169,7 +169,7 @@</span><br><span> u8 Perm[MAX_NODES]; /* The node mapping from the database to the system */</span><br><span> u8 ReversePerm[MAX_NODES]; /* The node mapping from the system to the database */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Data for non-coherent initilization */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Data for non-coherent initialization */</span><br><span> u8 AutoBusCurrent;</span><br><span> u8 UsedCfgMapEntires;</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c</span><br><span>index 5f656f5..6542ae4 100644</span><br><span>--- a/src/northbridge/amd/amdht/h3ncmn.c</span><br><span>+++ b/src/northbridge/amd/amdht/h3ncmn.c</span><br><span>@@ -1116,7 +1116,7 @@</span><br><span> * @param[in] *nb = this northbridge</span><br><span> * @return = true - The link has the following status</span><br><span> * LinkCon = 1, Link is connected</span><br><span style="color: hsl(0, 100%, 40%);">- * InitComplete = 1,Link initilization is complete</span><br><span style="color: hsl(120, 100%, 40%);">+ * InitComplete = 1,Link initialization is complete</span><br><span> * NC = 1, Link is coherent</span><br><span> * UniP-cLDT = 0, Link is not Uniprocessor cLDT</span><br><span> * LinkConPend = 0 Link connection is not pending</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>index 4c33a2f..388f064 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>@@ -846,7 +846,7 @@</span><br><span> dword &= (0x1 << 7);</span><br><span> write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94, dword);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Restore DRAM Adddress/Timing Control Register */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Restore DRAM Address/Timing Control Register */</span><br><span> write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x04, data->f2x9cx04);</span><br><span> } else {</span><br><span> /* Disable PHY auto-compensation engine */</span><br><span>diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c</span><br><span>index 66730fc..3d9ff3e 100644</span><br><span>--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c</span><br><span>@@ -169,7 +169,7 @@</span><br><span> break;</span><br><span> case NV_SPDCHK_RESTRT:</span><br><span> val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */</span><br><span style="color: hsl(0, 100%, 40%);">- //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */</span><br><span style="color: hsl(120, 100%, 40%);">+ //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */</span><br><span> //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */</span><br><span> </span><br><span> if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS)</span><br><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index 0e95341..5af3e16 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -107,7 +107,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 MiB aligment. As this may cause very greedy MTRR setup, push</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span> * CBMEM top downwards to 4 MiB boundary.</span><br><span> */</span><br><span> void *cbmem_top(void)</span><br><span>diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c</span><br><span>index 15ba7f4..7ee7198 100644</span><br><span>--- a/src/northbridge/intel/i945/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/i945/ram_calc.c</span><br><span>@@ -59,7 +59,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 MiB aligment. As this may cause very greedy MTRR setup, push</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span> * CBMEM top downwards to 4 MiB boundary.</span><br><span> */</span><br><span> void *cbmem_top(void)</span><br><span>diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>index d116709..62855c2 100644</span><br><span>--- a/src/northbridge/intel/pineview/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>@@ -95,7 +95,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 MiB aligment. As this may cause very greedy MTRR setup, push</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span> * CBMEM top downwards to 4 MiB boundary.</span><br><span> */</span><br><span> void *cbmem_top(void)</span><br><span>diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>index 49afdc3..1f1c13f 100644</span><br><span>--- a/src/northbridge/intel/x4x/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/x4x/ram_calc.c</span><br><span>@@ -93,7 +93,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Depending of UMA and TSEG configuration, TSEG might start at any</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 MiB aligment. As this may cause very greedy MTRR setup, push</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push</span><br><span> * CBMEM top downwards to 4 MiB boundary.</span><br><span> */</span><br><span> void *cbmem_top(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27911">change 27911</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27911"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I00094028036f33892362b935899e1bceef1da625 </div>
<div style="display:none"> Gerrit-Change-Number: 27911 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>