<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27907">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/coffeelake_rvp: Update gpio table for Coffeelake U RVP<br><br>Update GPIO table for coffeelake U RVP board<br><br>Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c<br>1 file changed, 15 insertions(+), 24 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/27907/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>index 060b7f3d..ee6f0a3 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -16,9 +16,8 @@</span><br><span> #include <baseboard/gpio.h></span><br><span> #include <baseboard/variants.h></span><br><span> #include <commonlib/helpers.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <compiler.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Pad configuration in ramstage*/</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)</span><br><span> static const struct pad_config gpio_table[] = {</span><br><span> /* GPPC */</span><br><span> /* A0 : RCINB_TIME_SYNC_1 */</span><br><span>@@ -43,14 +42,14 @@</span><br><span> /* A15 : SUSACKB */</span><br><span> PAD_CFG_GPO(GPP_A15, 1, PLTRST),</span><br><span> /* A16 : SD_1P8_SEL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_A16, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST),</span><br><span> /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */</span><br><span> /* A18 : ISH_GP_0 */</span><br><span> PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),</span><br><span> /* A19 : ISH_GP_1 */</span><br><span> PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A20 : aduio codec irq */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A20 : ISH_GP_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A20, UP_20K, DEEP, NF1),</span><br><span> /* A21 : ISH_GP_3 */</span><br><span> PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),</span><br><span> /* A22 : ISH_GP_4 */</span><br><span>@@ -110,7 +109,7 @@</span><br><span> /* C10 : UART0_RTSB */</span><br><span> PAD_CFG_GPO(GPP_C10, 0, PLTRST),</span><br><span> /* C11 : UART0_CTSB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_TERM_GPO(GPP_C11, 1, UP_20K, DEEP),</span><br><span> /* C12 : UART1_RXD_ISH_UART1_RXD */</span><br><span> PAD_CFG_GPO(GPP_C12, 1, PLTRST),</span><br><span> /* C13 : UART1_RXD_ISH_UART1_TXD */</span><br><span>@@ -138,7 +137,7 @@</span><br><span> /* D9 : ISH_SPI_CSB */</span><br><span> PAD_CFG_GPO(GPP_D9, 1, PLTRST),</span><br><span> /* D10 : ISH_SPI_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_D10, UP_20K, PLTRST, LEVEL, INVERT),</span><br><span> /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */</span><br><span> PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),</span><br><span> /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */</span><br><span>@@ -150,23 +149,15 @@</span><br><span> /* D16 : ISH_UART0_CTSB_SML0BALERTB */</span><br><span> PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),</span><br><span> /* D17 : DMIC_CLK_1_SNDW3_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),</span><br><span> /* D18 : DMIC_DATA_1_SNDW3_DATA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),</span><br><span> /* D19 : DMIC_CLK_0_SNDW4_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),</span><br><span> /* D20 : DMIC_DATA_0_SNDW4_DATA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),</span><br><span> /* D21 : SPI1_IO_2 */</span><br><span> PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),</span><br><span> /* D22 : SPI1_IO_3 */</span><br><span> PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),</span><br><span> /* D23 : SPP_MCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E0 : SATAXPCIE_0_SATAGP_0 */</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVP11)</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* E1 : SATAXPCIE_1_SATAGP_1 */</span><br><span> /* E2 : SATAXPCIE_2_SATAGP_2 */</span><br><span> PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),</span><br><span>@@ -247,9 +238,7 @@</span><br><span> /* H4 : I2C2_SDA */</span><br><span> /* H5 : I2C2_SCL */</span><br><span> /* H6 : I2C3_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1),</span><br><span> /* H7 : I2C3_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1),</span><br><span> /* H8 : I2C4_SDA */</span><br><span> /* H9 : I2C4_SCL */</span><br><span> /* H10 : I2C5_SDA_ISH_I2C2_SDA */</span><br><span>@@ -261,7 +250,7 @@</span><br><span> /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */</span><br><span> PAD_CFG_GPO(GPP_H13, 1, PLTRST),</span><br><span> /* H14 : M2_SKT2_CFG_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H14, 0, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H14, 1, PLTRST),</span><br><span> /* H15 : M2_SKT2_CFG_3 */</span><br><span> PAD_CFG_GPO(GPP_H15, 1, PLTRST),</span><br><span> /* H16 : CAM5_PWR_EN */</span><br><span>@@ -274,7 +263,7 @@</span><br><span> /* H20 : IMGCLKOUT_1 */</span><br><span> /* H21 : GPPC_H_21 */</span><br><span> /* H22 : GPPC_H_22 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H22, 1, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPP_H22, NONE, DEEP),</span><br><span> /* H23 : GPPC_H_23 */</span><br><span> </span><br><span> /* GPD */</span><br><span>@@ -290,7 +279,9 @@</span><br><span> /* GPD-9 : SLP_WLANB */</span><br><span> /* GPD-10 : SLP_5B */</span><br><span> /* GPD_11 : LANPHYPC */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> };</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> /* Early pad configuration in bootblock */</span><br><span> static const struct pad_config early_gpio_table[] = {</span><br><span>@@ -298,13 +289,13 @@</span><br><span> </span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct pad_config *__weak variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)</span><br><span> {</span><br><span> *num = ARRAY_SIZE(gpio_table);</span><br><span> return gpio_table;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct pad_config *__weak</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__attribute__((weak))</span><br><span> variant_early_gpio_table(size_t *num)</span><br><span> {</span><br><span> *num = ARRAY_SIZE(early_gpio_table);</span><br><span>@@ -315,7 +306,7 @@</span><br><span> CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const struct cros_gpio * __weak variant_cros_gpios(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)</span><br><span> {</span><br><span> *num = ARRAY_SIZE(cros_gpios);</span><br><span> return cros_gpios;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27907">change 27907</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27907"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d </div>
<div style="display:none"> Gerrit-Change-Number: 27907 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>