<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27906">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/coffeelake_rvp: Update spd details as per Coffeelake board<br><br>Update SPD details to match with Coffeelake U RVP board<br><br>Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/romstage.c<br>M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c<br>2 files changed, 18 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/27906/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>index 2eefcca..29b1846 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>@@ -36,8 +36,8 @@</span><br><span> mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);</span><br><span> mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->DqPinsInterleaved = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->DqPinsInterleaved = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */</span><br><span> mem_cfg->ECT = 1; /* Early Command Training Enabled */</span><br><span> spd_index = 2;</span><br><span> </span><br><span>@@ -51,4 +51,10 @@</span><br><span> mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);</span><br><span> mem_cfg->RefClk = 0; /* Auto Select CLK freq */</span><br><span> mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Hard coding SpdAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[0] = 0xA0;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[1] = 0xA2;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[2] = 0xA4;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[3] = 0xA6;</span><br><span> }</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>index 09bd303..ece6b6c 100644</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -23,8 +23,8 @@</span><br><span> {</span><br><span> /* DQ byte map Ch0 */</span><br><span> const u8 dq_map[12] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 };</span><br><span> </span><br><span> memcpy(dq_map_ptr, dq_map, sizeof(dq_map));</span><br><span> }</span><br><span>@@ -32,8 +32,8 @@</span><br><span> void mainboard_fill_dq_map_ch1(void *dq_map_ptr)</span><br><span> {</span><br><span> const u8 dq_map[12] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 };</span><br><span> </span><br><span> memcpy(dq_map_ptr, dq_map, sizeof(dq_map));</span><br><span> }</span><br><span>@@ -41,27 +41,17 @@</span><br><span> void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)</span><br><span> {</span><br><span> /* DQS CPU<>DRAM map Ch0 */</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));</span><br><span> }</span><br><span> </span><br><span> void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)</span><br><span> {</span><br><span> /* DQS CPU<>DRAM map Ch1 */</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_h[8] = { 1, 0, 4, 5, 2, 3, 6, 7 };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));</span><br><span> }</span><br><span> </span><br><span> void mainboard_fill_rcomp_res_data(void *rcomp_ptr)</span><br><span>@@ -75,7 +65,7 @@</span><br><span> {</span><br><span> /* Rcomp target */</span><br><span> static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 80, 40, 40, 40, 30 };</span><br><span style="color: hsl(120, 100%, 40%);">+ 100, 33, 32, 33, 28 };</span><br><span> </span><br><span> memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27906">change 27906</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246 </div>
<div style="display:none"> Gerrit-Change-Number: 27906 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>