<p><a href="https://review.coreboot.org/27911">View Change</a></p><p>7 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdfam10/amdfam10.h">File src/northbridge/amd/amdfam10/amdfam10.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdfam10/amdfam10.h@371">Patch Set #1, Line 371:</a> <code style="font-family:monospace,monospace">   for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdfam10/amdfam10.h@372">Patch Set #1, Line 372:</a> <code style="font-family:monospace,monospace">   for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdfam10/amdfam10.h@373">Patch Set #1, Line 373:</a> <code style="font-family:monospace,monospace">                                         F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdht/h3ffeat.h">File src/northbridge/amd/amdht/h3ffeat.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdht/h3ffeat.h@160">Patch Set #1, Line 160:</a> <code style="font-family:monospace,monospace">     /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdht/h3ncmn.c">File src/northbridge/amd/amdht/h3ncmn.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdht/h3ncmn.c@1119">Patch Set #1, Line 1119:</a> <code style="font-family:monospace,monospace"> *                                     InitComplete = 1,Link initialization is complete</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c">File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@849">Patch Set #1, Line 849:</a> <code style="font-family:monospace,monospace">                          /* Restore DRAM Address/Timing Control Register */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdmct/wrappers/mcti_d.c">File src/northbridge/amd/amdmct/wrappers/mcti_d.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdmct/wrappers/mcti_d.c@172">Patch Set #1, Line 172:</a> <code style="font-family:monospace,monospace">           //val = 1;      /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/27911">change 27911</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27911"/><meta itemprop="name" content="View Change"/></div></div>

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<div style="display:none"> Gerrit-Change-Id: I00094028036f33892362b935899e1bceef1da625 </div>
<div style="display:none"> Gerrit-Change-Number: 27911 </div>
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<div style="display:none"> Gerrit-Comment-Date: Tue, 07 Aug 2018 10:27:36 +0000 </div>
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