<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27918">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/cpu: Fix typo<br><br>Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/fsp_model_206ax/finalize.c<br>M src/cpu/intel/haswell/finalize.c<br>M src/cpu/intel/model_2065x/finalize.c<br>M src/cpu/intel/model_206ax/finalize.c<br>M src/cpu/x86/16bit/entry16.inc<br>5 files changed, 5 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27918/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c</span><br><span>index 53a6cc9..2d5973b 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/finalize.c</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/finalize.c</span><br><span>@@ -69,7 +69,7 @@</span><br><span> msr_set_bit(MSR_PP1_POWER_LIMIT, 31);</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock TM interupts - route thermal events to all processors */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lock TM interrupts - route thermal events to all processors */</span><br><span> msr_set_bit(MSR_MISC_PWR_MGMT, 22);</span><br><span> </span><br><span> /* Lock memory configuration to protect SMM */</span><br><span>diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c</span><br><span>index ba25387..ce22e62 100644</span><br><span>--- a/src/cpu/intel/haswell/finalize.c</span><br><span>+++ b/src/cpu/intel/haswell/finalize.c</span><br><span>@@ -72,7 +72,7 @@</span><br><span> msr_set_bit(MSR_PP1_POWER_LIMIT, 31);</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock TM interupts - route thermal events to all processors */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lock TM interrupts - route thermal events to all processors */</span><br><span> msr_set_bit(MSR_MISC_PWR_MGMT, 22);</span><br><span> </span><br><span> /* Lock memory configuration to protect SMM */</span><br><span>diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c</span><br><span>index 5e7b3d8..8425f6a 100644</span><br><span>--- a/src/cpu/intel/model_2065x/finalize.c</span><br><span>+++ b/src/cpu/intel/model_2065x/finalize.c</span><br><span>@@ -52,6 +52,6 @@</span><br><span> if (cpuid_ecx(1) & (1 << 25))</span><br><span> msr_set_bit(MSR_FEATURE_CONFIG, 0);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock TM interupts - route thermal events to all processors */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lock TM interrupts - route thermal events to all processors */</span><br><span> msr_set_bit(MSR_MISC_PWR_MGMT, 22);</span><br><span> }</span><br><span>diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c</span><br><span>index 50f4977..7d3cc2e 100644</span><br><span>--- a/src/cpu/intel/model_206ax/finalize.c</span><br><span>+++ b/src/cpu/intel/model_206ax/finalize.c</span><br><span>@@ -70,7 +70,7 @@</span><br><span> msr_set_bit(MSR_PP1_POWER_LIMIT, 31);</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock TM interupts - route thermal events to all processors */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lock TM interrupts - route thermal events to all processors */</span><br><span> msr_set_bit(MSR_MISC_PWR_MGMT, 22);</span><br><span> </span><br><span> /* Lock memory configuration to protect SMM */</span><br><span>diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc</span><br><span>index a87ce75..5a9739c 100644</span><br><span>--- a/src/cpu/x86/16bit/entry16.inc</span><br><span>+++ b/src/cpu/x86/16bit/entry16.inc</span><br><span>@@ -89,7 +89,7 @@</span><br><span> * must be loaded at or above 0xffff0000 or below 0x100000.</span><br><span> *</span><br><span> * The linker scripts computes gdtptr16_offset by simply returning</span><br><span style="color: hsl(0, 100%, 40%);">- * the low 16 bits. This means that the intial segment used</span><br><span style="color: hsl(120, 100%, 40%);">+ * the low 16 bits. This means that the initial segment used</span><br><span> * when start is called must be 64K aligned. This should not</span><br><span> * restrict the address as the ip address can be anything.</span><br><span> *</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27918">change 27918</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27918"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb </div>
<div style="display:none"> Gerrit-Change-Number: 27918 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>