<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27924">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Add warm reset detection<br><br>Extend the existing reset handling features in Stoney Ridge to plan for,<br>and recognize, warm resets. The ColdRstDet bit is always zero on a cold<br>reset, and is intended as a mechanism for the BIOS to determine the type<br>of a reset that occurred.<br><br>Set ColdRstDet=1 after all cores have been initialized, so that any<br>subsequent reset may be identified as warm/cold. A later patch will check<br>the value during mp_init.<br><br>Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/cpu.c<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/reset.c<br>3 files changed, 21 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/27924/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c</span><br><span>index 7fff120..52b1c9c 100644</span><br><span>--- a/src/soc/amd/stoneyridge/cpu.c</span><br><span>+++ b/src/soc/amd/stoneyridge/cpu.c</span><br><span>@@ -113,6 +113,8 @@</span><br><span> </span><br><span> /* The flash is now no longer cacheable. Reset to WP for performance. */</span><br><span> mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ set_warm_reset_flag();</span><br><span> }</span><br><span> </span><br><span> static void model_15_init(struct device *dev)</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index 666be10..56ae363 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -30,6 +30,7 @@</span><br><span> # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */</span><br><span> #define HT_INIT_CONTROL 0x6c</span><br><span> # define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10))</span><br><span style="color: hsl(120, 100%, 40%);">+# define HTIC_COLD_RST_DET BIT(4)</span><br><span> </span><br><span> /* NB IOAPIC registers */</span><br><span> #define NB_IOAPIC_INDEX 0xf8</span><br><span>@@ -116,5 +117,7 @@</span><br><span> void nb_ioapic_write(unsigned int index, uint32_t value);</span><br><span> void *get_ap_entry_ptr(void);</span><br><span> void set_ap_entry_ptr(void *entry);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_warm_reset_flag(void);</span><br><span style="color: hsl(120, 100%, 40%);">+int is_warm_reset(void);</span><br><span> </span><br><span> #endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */</span><br><span>diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c</span><br><span>index a133a88..738ec59 100644</span><br><span>--- a/src/soc/amd/stoneyridge/reset.c</span><br><span>+++ b/src/soc/amd/stoneyridge/reset.c</span><br><span>@@ -21,6 +21,21 @@</span><br><span> #include <device/pci_ops.h></span><br><span> #include <soc/southbridge.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void set_warm_reset_flag(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 htic;</span><br><span style="color: hsl(120, 100%, 40%);">+ htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ htic |= HTIC_COLD_RST_DET;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int is_warm_reset(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 htic;</span><br><span style="color: hsl(120, 100%, 40%);">+ htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ return !!(htic & HTIC_COLD_RST_DET);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Clear bits 5, 9 & 10, used to signal the reset type */</span><br><span> static void clear_bios_reset(void)</span><br><span> {</span><br><span>@@ -42,6 +57,7 @@</span><br><span> </span><br><span> void do_soft_reset(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ set_warm_reset_flag();</span><br><span> clear_bios_reset();</span><br><span> </span><br><span> /* Assert reset signals only. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27924">change 27924</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e </div>
<div style="display:none"> Gerrit-Change-Number: 27924 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Marshall Dawson <marshall.dawson@scarletltd.com> </div>