<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27923">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/amd: Correct number of MCA banks cleared<br><br>Use the value discovered in the MCG_CAP[Count] for the number of MCA<br>status registers to clear. The generations should have the following<br>number of banks:<br> * Family 10h: 6 banks<br> * Family 12h: 6<br> * Family 14h: 6<br> * Family 15h: 7<br> * Family 16h: 6<br><br>Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/cpu/amd/agesa/family12/model_12_init.c<br>M src/cpu/amd/agesa/family14/model_14_init.c<br>M src/cpu/amd/agesa/family15tn/model_15_init.c<br>M src/cpu/amd/agesa/family16kb/model_16_init.c<br>M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>M src/cpu/amd/pi/00630F01/model_15_init.c<br>M src/cpu/amd/pi/00660F01/model_15_init.c<br>M src/cpu/amd/pi/00730F01/model_16_init.c<br>M src/include/cpu/amd/amdfam15.h<br>M src/include/cpu/amd/amdfam16.h<br>M src/soc/amd/stoneyridge/cpu.c<br>11 files changed, 46 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/27923/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c</span><br><span>index afdfb3b..d38a8f3 100644</span><br><span>--- a/src/cpu/amd/agesa/family12/model_12_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family12/model_12_init.c</span><br><span>@@ -27,6 +27,8 @@</span><br><span> #include <cpu/amd/multicore.h></span><br><span> #include <cpu/amd/amdfam12.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MCG_CAP 0x179</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_BANKS_MASK 0xff</span><br><span> #define MC0_STATUS 0x401</span><br><span> </span><br><span> static void model_12_init(struct device *dev)</span><br><span>@@ -35,6 +37,7 @@</span><br><span> </span><br><span> u8 i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i num_banks;</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span> u32 siblings;</span><br><span>@@ -52,9 +55,11 @@</span><br><span> disable_cache();</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 5; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++) {</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>index 257f81f..fc4227a 100644</span><br><span>--- a/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family14/model_14_init.c</span><br><span>@@ -28,12 +28,15 @@</span><br><span> #include <arch/acpi.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MCG_CAP 0x179</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_BANKS_MASK 0xff</span><br><span> #define MC0_STATUS 0x401</span><br><span> </span><br><span> static void model_14_init(struct device *dev)</span><br><span> {</span><br><span> u8 i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span> int msrno;</span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span> u32 siblings;</span><br><span>@@ -75,9 +78,11 @@</span><br><span> x86_enable_cache();</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 6; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++) {</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>index 1e0375f..d579a5a 100644</span><br><span>--- a/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c</span><br><span>@@ -35,6 +35,7 @@</span><br><span> </span><br><span> u8 i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span> int msrno;</span><br><span> unsigned int cpu_idx;</span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span>@@ -72,9 +73,11 @@</span><br><span> x86_enable_cache();</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 6; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++) {</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>index 9909793..0c584f7 100644</span><br><span>--- a/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c</span><br><span>@@ -34,6 +34,7 @@</span><br><span> </span><br><span> u8 i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span> int msrno;</span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span> u32 siblings;</span><br><span>@@ -70,9 +71,11 @@</span><br><span> x86_enable_cache();</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 6; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++) {</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>index 61eb813..acc65e2 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c</span><br><span>@@ -32,6 +32,8 @@</span><br><span> #include <cpu/amd/multicore.h></span><br><span> #include <cpu/amd/msr.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MCG_CAP 0x179</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_BANKS_MASK 0xff</span><br><span> #define MC0_STATUS 0x401</span><br><span> </span><br><span> static inline uint8_t is_gt_rev_d(void)</span><br><span>@@ -62,6 +64,7 @@</span><br><span> {</span><br><span> u8 i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span> struct node_core_id id;</span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span> u32 siblings;</span><br><span>@@ -109,9 +112,11 @@</span><br><span> disable_cache();</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 5; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++) {</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>index 592ca4f..0269a1e 100644</span><br><span>--- a/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>+++ b/src/cpu/amd/pi/00630F01/model_15_init.c</span><br><span>@@ -35,6 +35,7 @@</span><br><span> </span><br><span> u8 i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span> int msrno;</span><br><span> unsigned int cpu_idx;</span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span>@@ -69,9 +70,11 @@</span><br><span> x86_enable_cache();</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 6; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++)</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> </span><br><span> /* Enable the local CPU APICs */</span><br><span>diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>index 24c2aea..424a6c0 100644</span><br><span>--- a/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>+++ b/src/cpu/amd/pi/00660F01/model_15_init.c</span><br><span>@@ -51,6 +51,7 @@</span><br><span> </span><br><span> u8 i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span> int msrno;</span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span> u32 siblings;</span><br><span>@@ -81,12 +82,13 @@</span><br><span> x86_enable_cache();</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 6; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++)</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable the local CPU APICs */</span><br><span> setup_lapic();</span><br><span> </span><br><span>diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>index b9e0185..160d6d8 100644</span><br><span>--- a/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>+++ b/src/cpu/amd/pi/00730F01/model_16_init.c</span><br><span>@@ -34,6 +34,7 @@</span><br><span> </span><br><span> u8 i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span> int msrno;</span><br><span> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)</span><br><span> u32 siblings;</span><br><span>@@ -66,12 +67,13 @@</span><br><span> x86_enable_cache();</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 6; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < num_banks; i++)</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Enable the local CPU APICs */</span><br><span> setup_lapic();</span><br><span> </span><br><span>diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h</span><br><span>index c28ec13..3095dd1 100644</span><br><span>--- a/src/include/cpu/amd/amdfam15.h</span><br><span>+++ b/src/include/cpu/amd/amdfam15.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef CPU_AMD_FAM15_H</span><br><span> #define CPU_AMD_FAM15_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MCG_CAP 0x00000179</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_BANKS_MASK 0xff</span><br><span> #define MC0_STATUS 0x00000401</span><br><span> #define MSR_SMM_BASE 0xC0010111</span><br><span> #define MSR_TSEG_BASE 0xC0010112</span><br><span>diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h</span><br><span>index 8d8be83..8b7503d 100644</span><br><span>--- a/src/include/cpu/amd/amdfam16.h</span><br><span>+++ b/src/include/cpu/amd/amdfam16.h</span><br><span>@@ -16,6 +16,8 @@</span><br><span> #ifndef CPU_AMD_FAM16_H</span><br><span> #define CPU_AMD_FAM16_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MCG_CAP 0x00000179</span><br><span style="color: hsl(120, 100%, 40%);">+# define MCA_BANKS_MASK 0xff</span><br><span> #define MC0_STATUS 0x00000401</span><br><span> #define HWCR_MSR 0xC0010015</span><br><span> #define NB_CFG_MSR 0xC001001f</span><br><span>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c</span><br><span>index 6289174..7fff120 100644</span><br><span>--- a/src/soc/amd/stoneyridge/cpu.c</span><br><span>+++ b/src/soc/amd/stoneyridge/cpu.c</span><br><span>@@ -121,11 +121,14 @@</span><br><span> </span><br><span> int i;</span><br><span> msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span> </span><br><span> /* zero the machine check error status registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & MCA_BANKS_MASK;</span><br><span> msr.lo = 0;</span><br><span> msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0 ; i < 6 ; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0 ; i < num_banks ; i++)</span><br><span> wrmsr(MC0_STATUS + (i * 4), msr);</span><br><span> </span><br><span> setup_lapic();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27923">change 27923</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 </div>
<div style="display:none"> Gerrit-Change-Number: 27923 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>