<p>Aamir Bohra has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27889">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/intel/common: Configure the chip select state correctly<br><br>This implementation updates the chip select control register<br>programming in gspi controller setup call to program the correct<br>bit fields for chip select state.<br><br>Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53<br>Signed-off-by: Aamir Bohra <aamir.bohra@intel.com><br>---<br>M src/soc/intel/common/block/gspi/gspi.c<br>1 file changed, 1 insertion(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27889/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c</span><br><span>index 35c34ce..fc7dd46 100644</span><br><span>--- a/src/soc/intel/common/block/gspi/gspi.c</span><br><span>+++ b/src/soc/intel/common/block/gspi/gspi.c</span><br><span>@@ -481,12 +481,9 @@</span><br><span>        cs_ctrl = CS_MODE_SW | CS_0;</span><br><span>         pol = gspi_csctrl_polarity(cfg.cs_polarity);</span><br><span>         cs_ctrl |= pol << CS_0_POL_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT);</span><br><span style="color: hsl(120, 100%, 40%);">+       cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT) << CS_STATE_SHIFT;</span><br><span>      gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-    /* De-assert chip select. */</span><br><span style="color: hsl(0, 100%, 40%);">-    __gspi_cs_change(p, CS_DEASSERT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>    /* Disable SPI controller. */</span><br><span>        gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27889">change 27889</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27889"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 </div>
<div style="display:none"> Gerrit-Change-Number: 27889 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Aamir Bohra <aamir.bohra@intel.com> </div>